High-Temperature Impact-Ionization Model for 4H-SiC

Nida, Selamnesh; Großner, Ulrike

doi:10.1109/ted.2019.2899285

Cited by 20 publications

(3 citation statements)

References 32 publications

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“…Different physical models impact the final results. Especially for the impact ionization coefficient predicated by different models [21,22,28,29], the difference could be some magnitudes in 4H-SiC in our studied temperature range. So the study of practical devices is necessary in the future.…”

Section: Discussionmentioning

confidence: 76%

Simulation of the 4H-SiC Low Gain Avalanche Diode

Yang¹,

Tan²,

Wang³

et al. 2022

Preprint

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Silicon Carbide device (4H-SiC) has potential radiation hardness, high saturated carrier velocity and low temperature sensitivity theoretically. The Silicon Low Gain Avalanche Diode (LGAD) has been verified to have excellent time performance. Therefore, the 4H-SiC LGAD is introduced in this work for application to detect the Minimum Ionization Particles (MIPs). We provide guidance to determine the thickness and doping level of the gain layer after an analytical analysis. The gain layer thickness d gain = 0.5 µm is adopted in our design. We design two different types of 4H-SiC LGAD which have two types electric field, and the corresponding leakage current, capacitance and gain are simulated by TCAD tools. Through analysis of the simulation results, the advantages and disadvantages are discussed for two types of 4H-SiC LGAD.

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Section: Discussionmentioning

confidence: 76%

Simulation of the 4H-SiC Low Gain Avalanche Diode

Yang¹,

Tan²,

Wang³

et al. 2022

Preprint

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“…This study adopted the Shockley-Read-Hall (SRH) and Auger recombination models, as well as the Canali model for high-field saturation and the Okuto model for impact ionization. For SiC material properties, anisotropic mobility and incomplete ionization were considered [21]. The displacement defect was modeled with six different energy levels in SiC materials: 0.69, 0.72, 0.88, 1.03, 1.08, and 1.55 eV below conduction band edge (E C ) [16].…”

Section: Simulation Modeling Methodologymentioning

confidence: 99%

Influence of Radiation-Induced Displacement Defect in 1.2 kV SiC Metal-Oxide-Semiconductor Field-Effect Transistors

Lee

Kim

et al. 2022

Micromachines

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The effect of displacement defect on SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) due to radiation is investigated using technology computer-aided design (TCAD) simulation. The position, energy level, and concentration of the displacement defect are considered as variables. The transfer characteristics, breakdown voltage, and energy loss of a double-pulse switching test circuit are analyzed. Compared with the shallow defect energy level, the deepest defect energy level with EC − 1.55 eV exhibits considerable degradation. The on-current decreases by 54% and on-resistance increases by 293% due to the displacement defect generated at the parasitic junction field-effect transistor (JFET) region next to the P-well. Due to the existence of a defect in the drift region, the breakdown voltage increased up to 21 V. In the double-pulse switching test, the impact of displacement defect on the power loss of SiC MOSFETs is negligible.

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“…The BVs of the conventional SiC LDMOS at the temperature of 300K and 400K are about 1210V and 1240V, while the proposed SiC LDMOS are about 1460 V and 1490 V at 300K and 400K, respectively. The positive temperature coefficient of the BV of the SiC LDMOS device is due to the competing phonon scattering mechanisms that reduce the rate of the impact ionization [26], [27]. The reason for the higher BV of the proposed LDMOS device than the conventional LDMOS device is the introduction of the VLD technique in the drift region of the proposed LDMOS, which results in a flatter surface electric field distribution in the drift region of the semiconductor surface.…”

Section: ⅱ Device Structure and Mechanismmentioning

confidence: 99%

A 1200-V-Class Ultra-Low Specific On-Resistance SiC Lateral MOSFET With Double Trench Gate and VLD Technique

Kong

Gao

et al. 2022

IEEE J. Electron Devices Soc.

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An ultra-low specific on-resistance 4H-SiC power laterally diffused metal oxide semiconductor (LDMOS) device is proposed for 1200V-class applications. In the proposed SiC LDMOS device, a double-trench gate is introduced to reduce the channel region resistance. And a p-type variation lateral doping (VLD) region is also employed in the drift region, which not only optimizes the surface electric field and improves the breakdown voltage, but also increases the doping concentration of the N-drift region, resulting in a low drift region resistance. So that, the proposed device achieves an ultra-low specific on-resistance (Ron,sp). Numerical Simulation results show that the Ron,sp of the proposed SiC LDMOS is 3.5 mΩcm 2 with a breakdown voltage of ～1460V, which is reduced by more than 46% compared with the conventional field-plate SiC LDMOS with a Ron,sp of 6.6 mΩcm 2 and a breakdown voltage of ～ 1210V. The transconductance of the proposed device is improved greatly. And the trade-off relationship between the Ron,sp and the breakdown voltage is also significantly improved compared with those of the conventional device and the previous literature.

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High-Temperature Impact-Ionization Model for 4H-SiC

Cited by 20 publications

References 32 publications

Simulation of the 4H-SiC Low Gain Avalanche Diode

Simulation of the 4H-SiC Low Gain Avalanche Diode

Influence of Radiation-Induced Displacement Defect in 1.2 kV SiC Metal-Oxide-Semiconductor Field-Effect Transistors

A 1200-V-Class Ultra-Low Specific On-Resistance SiC Lateral MOSFET With Double Trench Gate and VLD Technique

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