High throughput 2D DCT/IDCT processor for video coding

Abstract

This paper describes the architecture of an 8x8 2-D DCT/IDCT processor with high throughput, reduced hardware, and a parallel-pipeline scheme. This architecture allows the processing elements and arithmetic units to work in parallel at half the frequency of the data input rate. A fully pipelined row-column decomposition method based on two 1-D DCTs and a transpose buffer based on D-type flip-flops are used. The processor has been implemented in a 0.35-µm CMOS process with a core area of 3mm 2 and 11.7k gates. It meets the requirements of IEEE Std. . The data input rate frequency is 300MHz with a latency of 172 cycles for 2-D DCT and 178 cycles for 2-D IDCT. The proposed design is compact and suitable for HDTV applications.

High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip

“…Table 2 shows the hardware cost in terms of number of gates for the different blocks of this processor. More details about chip implementation can be found in [22]. A maximum operating frequency of about 300 MHz has been established.…”

“…This paper describes the architecture of an 8Â8 2-D DCT/IDCT processor chip with a high throughput and a cost-effective architecture [22]. The 2D DCT/IDCT is calculated using the separability property, so that its architecture is made up of two 1-D processors and a transpose buffer (TB) as intermediate memory.…”