High throughput architecture for high performance NoC

Ghany, Mohamed A. Abd El; El-Moursy, Magdy A.; Ismail, Mohammed

doi:10.1109/iscas.2009.5118244

Cited by 15 publications

(2 citation statements)

References 33 publications

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“…A key element to address these challenges is a Network-on-Chip (NoC) topology that can manage the large volume of packets generated by Neural Networks. There are several topologies available, such as Tree topology [18], Butterfly Fat-tree [19], Octagon [20], Mesh topology, etc. The Mesh topology is the most widely used [21,22], due to its several advantages.…”

Section: Related Workmentioning

confidence: 99%

A Novel NoC-Based Neural Networks Design for Implementation of A Biosensor Solution

et al. 2023

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Graphene-based nanosensors are used in many applications to monitor and survey physical or chemical phenomena. The use of Graphene improves the mechanical, electrochemical, optical, and magnetic properties of nanosensors due to its properties such as physical properties. But there are some characteristics and measurements that must be taken to manufacture such sensors. In this work, a Neural Network (NN) has been proposed that can predict the values of UV (ultraviolet) measurements, which are wavelength and absorption, based on XRD (X Ray Diffraction) measurements, namely diameter (in millimeters) and angle (theta in degrees). The proposed NN was developed on Network-on-Chip (NoC) to take advantage of the high level of parallelism and computing power provided by NoC. In addition, we used an adaptive XY routing algorithm due to its simplicity and allows exploiting multiple paths to route packets to their destination which reduces the number of lost packets due to the high injection rate without introducing any latency. Moreover, we proposed a mapping algorithm to extract maximum performance from the adaptive XY algorithm. The obtained results show the efficiency of the proposed architecture, as it allows packets to take different paths. Thus, the traffic is distributed across the network and significantly reduces packet loss. Moreover, the equal length of these paths allows avoidance of latency. HIGHLIGHTS Network-on-chip (NoC) is a powerful tool for implementing artificial neural networks, thanks to its high level of parallelism and computing power The Adaptive XY algorithm eliminates the need for a routing table and allows traffic to be distributed over the NoC The proposed mapping algorithm allows for better traffic management within the NoC, thereby enhancing performance in terms of reducing lost packets GRAPHICAL ABSTRACT

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Section: Related Workmentioning

confidence: 99%

A Novel NoC-Based Neural Networks Design for Implementation of A Biosensor Solution

et al. 2023

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“…The network-on-chip (NoC) scheme for the complex communication requirements provides scalable and flexible communication for massively parallel systems [ 13 ]. NoCs have overcome scalability limitations by providing a flexible communication structure with high performance [ 14 , 15 ]. In addition, the authors of [ 16 , 17 ] present that unlike the shared bus topology, which cannot provide a dense interconnection for neural networks, the NoC scheme can provide high scalability with low power consumption by eliminating the one-to-one correspondence between nodes, in addition to reconfigurability.…”

Section: Introductionmentioning

confidence: 99%

Design of Network-on-Chip-Based Restricted Coulomb Energy Neural Network Accelerator on FPGA Device

Kang,

Lee,

Jung

2024

Sensors

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Sensor applications in internet of things (IoT) systems, coupled with artificial intelligence (AI) technology, are becoming an increasingly significant part of modern life. For low-latency AI computation in IoT systems, there is a growing preference for edge-based computing over cloud-based alternatives. The restricted coulomb energy neural network (RCE-NN) is a machine learning algorithm well-suited for implementation on edge devices due to its simple learning and recognition scheme. In addition, because the RCE-NN generates neurons as needed, it is easy to adjust the network structure and learn additional data. Therefore, the RCE-NN can provide edge-based real-time processing for various sensor applications. However, previous RCE-NN accelerators have limited scalability when the number of neurons increases. In this paper, we propose a network-on-chip (NoC)-based RCE-NN accelerator and present the results of implementation on a field-programmable gate array (FPGA). NoC is an effective solution for managing massive interconnections. The proposed RCE-NN accelerator utilizes a hierarchical–star (H–star) topology, which efficiently handles a large number of neurons, along with routers specifically designed for the RCE-NN. These approaches result in only a slight decrease in the maximum operating frequency as the number of neurons increases. Consequently, the maximum operating frequency of the proposed RCE-NN accelerator with 512 neurons increased by 126.1% compared to a previous RCE-NN accelerator. This enhancement was verified with two datasets for gas and sign language recognition, achieving accelerations of up to 54.8% in learning time and up to 45.7% in recognition time. The NoC scheme of the proposed RCE-NN accelerator is an appropriate solution to ensure the scalability of the neural network while providing high-performance on-chip learning and recognition.

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Cycle-accurate multi-FPGA platform for accelerated emulation of large on-chip networks

Romanov,

Lerner,

Amerikanov

2024

J Supercomput

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High throughput architecture for high performance NoC

Cited by 15 publications

References 33 publications

A Novel NoC-Based Neural Networks Design for Implementation of A Biosensor Solution

A Novel NoC-Based Neural Networks Design for Implementation of A Biosensor Solution

Design of Network-on-Chip-Based Restricted Coulomb Energy Neural Network Accelerator on FPGA Device

Cycle-accurate multi-FPGA platform for accelerated emulation of large on-chip networks

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