High-Throughput FPGA-Based QC-LDPC Decoder Architecture

Abstract

We propose without loss of generality strategies to achieve a high-throughput FPGA-based architecture for a QC-LDPC code based on a circulant-1 identity matrix construction. We present a novel representation of the parity-check matrix (PCM) providing a multi-fold throughput gain. Splitting of the node processing algorithm enables us to achieve pipelining of blocks and hence layers. By partitioning the PCM into not only layers but superlayers we derive an upper bound on the pipelining depth for the compact representation. To validate the architecture, a decoder for the IEEE 802.11n (2012) [1] QC-LDPC is implemented on the Xilinx Kintex-7 FPGA with the help of the FPGA IP compiler [2] available in the NI LabVIEW TM Communication System Design Suite (CSDS TM ) which offers an automated and systematic compilation flow where an optimized hardware implementation from the LDPC algorithm was generated in approximately 3 minutes, achieving an overall throughput of 608Mb/s (at 260MHz). As per our knowledge this is the fastest implementation of the IEEE 802.11n QC-LDPC decoder using an algorithmic compiler.

LDPC Codes for Communication Systems: Coding Theoretic Perspective

“…The circulant matrices are also suitable for the hardware implementation of decoders, e.g., a highthroughput FPGA-based decoder shown in [75]. The construction and details for QC-LDPC codes are summarized in [42].…”

High Throughput and Resource Efficient Pipelined Decoder Designs for Projective Geometry LDPC Codes

“…This in turn makes the design comparatively expensive and hence, we have not used this method in our proposed designs. Some other implementations as stated in [24,34]; used DSP slices available on FPGA to compute ϕ(x). The main disadvantages in using DSP slices are -First, the resources are limited on FPGA.…”

Design Trade‐Offs for FPGA Implementation of LDPC Decoders

“…In the case of a layered decoder, two types of messages require memory storage: the AP-LLR messages and the check node messages. A typical layered LDPC decoder [29][30][31][32][33], depicted in Figure 5, contains the following components:…”

“…Field -Programmable Gate Arraymessage to the AP-LLR update, a comparator for updating the check node message, and the addition unit for the AP-LLR update [29][30][31][32]. Specific FPGA optimization can be implemented within the combined processing unit, which includes the use of the 6-input LUT within the CLB for comparator implementation-the comparator is implemented as ROM memories [30]-as well as the usage of the dedicated shift register chains for the implementation of the FIFOs.…”