High throughput FPGA implementation of Min-Sum LDPC Decoder Architecture for Wireless Communication Standards

Nikishkin, Pavel; Goriushkin, Ruslan; Vinogradov, Nikita; Likhobabin, Evgeny; Vityazev, Vladimir

doi:10.1109/dspa53304.2022.9790744

Cited by 2 publications

(1 citation statement)

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“…Overall, LDPC decoders are a powerful tool for improving communication reliability, but they come with challenges and advantages. While they require a large amount of computing power and can be difficult to store and transmit, they offer high levels of accuracy and are well-suited for use in noisy environments [80][81][82].…”

Section: Advantages and Challenges Of Ldpc Decodermentioning

confidence: 99%

Enhancing Data Communication Performance: A Comprehensive Review and Evaluation of LDPC Decoder Architectures

Subhi,

Al-Doori,

Alani

2023

ISI

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Error Correction Codes (ECCs) stand as a linchpin in ensuring data accuracy in wireless communication. As the landscape of modern communication standards continues to expand, there is a mounting inclination towards efficient ECC technologies, such as Low-Density Parity-Check codes (LDPCs). Distinguished by their near-capacity performance and low computational complexity, LDPCs are increasingly utilized in the successful encoding and decoding of data. This study undertakes an exploration of recent advancements in LDPC research, encompassing the analysis of decoding algorithms, architectures, applications, simulations, real-world implementations, and complexities across various hardware platforms. The central research problem addressed within this work is the identification of the most efficacious LDPC decoder implementation, with an emphasis placed on Field-Programmable Gate Array (FPGA) technology. From the outcomes of this study, the Min-Sum algorithm emerged as the favored choice for LDPC decoding, particularly within FPGA implementations. The selection of this algorithm is attributable to its simplicity and implementation feasibility, thus directly addressing the posed research problem. The inherent simplicity of the Min-Sum algorithm's structure renders it a practical choice for real-world applications. Further, its proficiency in error correction and compatibility with FPGA hardware underscore its potential for augmenting the reliability of data transmission in communication systems. The findings of this study advocate for the Min-Sum algorithm as a valuable asset in LDPC decoding, notably within FPGA implementations. This positions it as a promising candidate for optimizing data communication systems. The selection of FPGA as the implementation platform reaffirms its practicality and relevance in contemporary communication technology, thus offering a comprehensive solution to the identified research problem.

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Section: Advantages and Challenges Of Ldpc Decodermentioning

confidence: 99%