2015 9th International Symposium on Image and Signal Processing and Analysis (ISPA) 2015
DOI: 10.1109/ispa.2015.7306068
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High throughput hardware architectures for asymmetric numeral systems entropy coding

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Cited by 15 publications
(17 citation statements)
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“…• Has high-throughput implementations. For Field Programmable Gate Arrays (FPGA), encoder architectures were studied in [30] and decoder in [31], which can outperform Huffman decoding [32].…”
Section: B Asymmetric Numeral Systemsmentioning
confidence: 99%
See 3 more Smart Citations
“…• Has high-throughput implementations. For Field Programmable Gate Arrays (FPGA), encoder architectures were studied in [30] and decoder in [31], which can outperform Huffman decoding [32].…”
Section: B Asymmetric Numeral Systemsmentioning
confidence: 99%
“…For more in depth explanation of the ANS algorithm and hardware implementations, refer to [18], [30], [31].…”
Section: ) Tans Operationmentioning
confidence: 99%
See 2 more Smart Citations
“…In this manuscript, we study Tabled ANS (tANS), which is an ANS variant that is well suited for hardware implementations [31], [32], [33]. It employs a finite state machine that transitions from state to state as symbols are encoded, which is certainly not a new idea [34].…”
Section: Introductionmentioning
confidence: 99%