High-throughput low-area design of AES using constant binary matrix-vector multiplication

Lee, Hokyoon; Paik, Yoonah; Jun, Jaeyung; Han, Youngsun; Kim, Seon Wook

doi:10.1016/j.micpro.2016.10.003

Cited by 13 publications

(15 citation statements)

References 2 publications

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“…Composite field and combinational logic strategy for s-box execution are compared within the foundation of area and throughput. To decrease the employed area, Lee et al [18] employed a sequence of continuous binary matrix multiplication rather of Galois field (GF) (28) calculation. Additionally, a four-step pipelined execution is also offered.…”

Section: Literature Reviewmentioning

confidence: 99%

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Advanced FPGA Implementation of AES Algorithm

2021

IJETER

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Along with the enhance in computation as well as information safe-keeping in cloud servers, the requirement for a devoted computer hardware accelerator with regard to encryption is arising to be able to decrease the processor work. Highly efficient Advanced Encryption Standard (AES) 128-bit implementation, that could be utilized as an accelerator. In this research paper resource optimization and higher throughput were obtained. Memory segmentation is actually carried out to be able to assign several ports for simultaneous information accessibility. When algorithm is in proceed and examined time delay and initiation time period of various procedures, with regard to every crucial route delay, a fresh multistage solitary initiation time period sub-pipelined structure is suggested for making the initiation time period to a single for smallest route latency. Consequently, almost all operations in AES could be started within a single clock cycle and also can easily accept input in each and every clock cycle. The suggested approach while examined on latest Field Programmable Gate Array (FPGA) XC7VX690T unit that offers a throughput of 104.06 Gbps at a highest frequency of 813MHz and also 1.23-ns route delay. The useful resource utilization is reduced whenever compared along with other alternatives. The suggested method offers 30.74Mbps efficiency on device, which usually was 27.13% much more compared to the best efficiency documented in an earlier research study

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Section: Literature Reviewmentioning

confidence: 99%

“…The objective is accomplished in the perform by sub-pipelining each procedure by having registers at suitable positions. In some other scientific studies [14,[16][17][18], the sub-pipelining is transported out by just managing the pipelining not targeted at producing the initiation interval to Just one.…”

Section: Smentioning

confidence: 99%

Advanced FPGA Implementation of AES Algorithm

2021

IJETER

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“…Optimization for speed and area are done through pipelining, sub-pipelining, loop unrolling, reducing the logic depth etc. [14][15][16][17][18][19][20]. Balancing between pipelining stages were done through allocation of registers at proper locations in order to avoid stalling.…”

Section: Fig 1 Overall View Of Hardware Acceleration Processmentioning

confidence: 99%

“…The authors used loop unrolling for critical path modification and fully pipelined and sub-pipelined techniques, which allowed the increase in the clock frequency and reduction in critical path. To reduce the area, Lee et al [18] employed a series of constant binary matrix multiplication instead of Galois field (GF) (28) computation. Good and Benaissa [19] presented two designs for AES feedback mode support.…”

Section: Fig 1 Overall View Of Hardware Acceleration Processmentioning

confidence: 99%

Improving Correctness of Logic Circuit using Self-Healing Built-In Logic Test Module in FPGA using Dynamic Partial Reconfiguration

C¹

2019

IJRTE

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As cloud servers continue to receive more and more applications and data, it starts using ASIC and FPGAs as accelerators for processor intensive applications. Because of the reconfiguration nature of FPGAs, it become a good choice rather than ASIC on cloud. Encryption is an application which happens frequently on cloud and takes lot of processor cycles which can be shifted to hardware accelerator for execution. The security of hardware circuit which is transferred as bitstream to the FPGA board is of major concern for security critical applications. The article proposes a novel logic authentication module that can check the authentication or correctness of selected parts of logic circuit any time after the circuit is burned into FPGA. In the proposed work, Advanced Encryption Standard (AES) circuit parts are checked for correctness by using in-built Secure Hash Algorithm (SHA) and corrected by Dynamic Partial Reconfiguration (DPR). After the bitstream is burned into FPGA, a proposed software module can select a part or entire circuit for checking authentication with multiple sample inputs. Without the proposed method, any error after the circuit creation cannot be identified or corrected. Additionally, small faults in the circuit is corrected by DPR without loading the entire module. Totally 16 Benchmarks were created to check the correctness of the proposed system. Usage of DPR for circuit correction saves about 97% of time compared to reconfiguring the entire module.

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“…Software implementations of the AES and PRESENT ciphers for low-cost smartphones have been compared in Andrés et al (2016) . Some of the popular complementary metal-oxide semiconductor (CMOS) application-specific integrated circuit (ASIC) implementations of the AES cipher on 180 nm technology include Dao et al (2016), Kuo and Verbauwhede (2001); Verbauwhede et al (2003), Kim et al (2003); Li (2006), Cao and Li (2009); Alma’Aitah and Abid (2010); Lee et al (2016), Van Lan et al (2018); and Cast (2019). AES as a coprocessor for embedded cryptographic and biometric applications has been designed and fabricated using TSMC 6 M 180 nm CMOS technology by Tiri et al (2005).…”

Section: Introductionmentioning

confidence: 99%

Design, integration and implementation of crypto cores in an SoC environment

Pandey

Gupta

Karmakar

2022

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Purpose The paper aims to develop a systematic approach to design, integrate, and implement a set of crypto cores in a system-on-chip SoC) environment for data security applications. The advanced encryption standard (AES) and PRESENT block ciphers are deployed together, leading to a common crypto chip for performing encryption and decryption operations. Design/methodology/approach An integrated very large-scale integration (VLSI) architecture and its implementation for the AES and PRESENT ciphers is proposed. As per the choice, the architecture performs encryption or decryption operations for the selected cipher. Experimental results of the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations and related design analysis are provided. Findings FPGA implementation of the architecture on Xilinx xc5vfx70t-1-ff1136 device consumes 19% slices, whereas the ASIC design is implemented in 180 nm complementary metal-oxide semiconductor ASIC technology that takes 1.0746 mm2 of standard cell area and consumes 14.26 mW of power at 50 MHz clock frequency. A secure audio application using the designed architecture on an open source SoC environment is also provided. A test methodology for validation of the designed chip using an FPGA-based platform and tools is discussed. Originality/value The proposed architecture is compared with a set of existing hardware architectures for analyzing various design metrics such as latency, area, maximum operating frequency, power, and throughput.

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High-throughput low-area design of AES using constant binary matrix-vector multiplication

Cited by 13 publications

References 2 publications

Advanced FPGA Implementation of AES Algorithm

Advanced FPGA Implementation of AES Algorithm

Improving Correctness of Logic Circuit using Self-Healing Built-In Logic Test Module in FPGA using Dynamic Partial Reconfiguration

Design, integration and implementation of crypto cores in an SoC environment

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