High-Throughput Low Power Area Efficient 17-bit 2’s Complement Multilayer Perceptron Components and Architecture for on-Chip Machine Learning in Implantable Devices

Abstract

In this manuscript the authors, design new hardware efficient combinational building blocks for a Multi Layer Perceptron (MLP) unit which eliminates the need for hardware generic Digital Signal Processing (DSP) units and also eliminates the need for on-chip block RAMs (BRAMs). The components were designed to minimise power and area consumption without sacrificing throughput. All designs were validated in a Field Programmable Gate Array (FPGA) and compared against unrestricted CPU-MATLAB implementations. Furthermore, a (2,2,2,2) MLP with back propagation was implemented and tested in a FPGA showing a total hardware utilisation of just 3782 LUTs, and no DSP or BRAMs. The MLP was also built in a Application Specific Integrated Circuit (ASIC) using a 130 nm technology by Skywater 130A. The results show that the area occupation was just 0.12 mm 2 and consumed just 100 mW at 100 MHz input stimulus.

Towards Flexible and Low-Power Wireless Smart Sensors: Reconfigurable Analog-to-Feature Conversion for Healthcare Applications

“…However, as indicated in Section 3.3, we can perform the classification directly within the sensor to diminish the amount of transmitted data further and send only the classification results. For this purpose, it is possible to implement at least a digital architecture of our simple feedforward NNs realized on a field programmable gate array (FPGA) [72][73][74], in an ASIC [74,75], or on a microcontroller [76,77].…”