This paper presents an integer-based digital processor for the calculation of phase synchronization between two neural signals. It is based on the measurement of time periods between two consecutive minima. The simplicity of the approach allows for the use of elementary digital blocks, such as registers, counters, and adders. The processor, fabricated in a 0.18-µm CMOS process, only occupies 0.05 mm 2 and consumes 15 nW from a 0.5 V supply voltage at a signal input rate of 1024 S/s. These low-area and low-power features make the proposed processor a valuable computing element in closed-loop neural prosthesis for the treatment of neural disorders, such as epilepsy, or for assessing the patterns of correlated activity in neural assemblies through the evaluation of functional connectivity maps.

This paper tackles the complex issue of detecting and classifying epileptic seizures whilst maintaining the total calculations at a minimum. Where many systems depend on the coupling between multiple sources, leading to hundreds of combinations of electrodes, our method calculates the instantaneous phase between non-identical upper and lower envelopes of a single-electroencephalography channel reducing the workload to the total number of electrode points. From over 600 h of simulations, our method shows a sensitivity and specificity of 100% for high false-positive rates and 83% and 75%, respectively, for moderate to low false positive rates, which compares well to both single- and multi-channel-based methods. Furthermore, pre-ictal variations in synchronisation were detected in over 90% of patients implying a possible prediction system.

This paper reports a low area, low power, integerbased neural digital processor for the calculation of phase synchronization between two neural signals. The processor calculates the phase-frequency content of a signal by identifying the specific time periods associated with two consecutive minima. The simplicity of this phase-frequency content identifier allows for the digital processor to utilize only basic digital blocks, such as registers, counters, adders and subtractors, without incorporating any complex multiplication and or division algorithms. The low area and power consumptions make the processor an extremely scalable device which would work well in closed loop neural prosthesis for the treatment of neural diseases.

This article introduces a new multiplier-less 32-bit fixed point architecture for estimating complex non-linear functions based on adapted shift only series expansions. This novel hardware structure has been proposed for use as a dedicated core unit in implantable medical devices. Its implementation in FPGA produces a mean squared error of 0.23% over the functions sin(x), cos(x), e ix and tan −1 (x) when compared to unrestricted CPU implementations. These results are achieved with the use of only 133 sliced registers and 399 Look-uptables (LUTs). Furthermore, the hardware performs extremely well in our hardware-in-the-loop real use case application for the detection of epilepsy by correctly detecting true positive seizures. When implemented into 130 nm technology via GOOGLE Sky130 PDK and Openlane EDA tools, the ASIC occupies a space of 0.0625 mm 2 which represents a 47% reduction when compared to competitors. In addition, its power consumption is reduced to 6.46 mW at 100 MHz f o and just 0.4 µW at 1KHz f o .