High-Throughput, Low-Power Software-Defined Radio Using Reconfigurable Processors

Suzuki, Tomoya; Yamada, Hideki; Yamagishi, T.; Takeda, Daisuke; Horisaki, Koji; Aa, Tom Vander; Fujisawa, Toshio; Perre, Liesbet Van der; Unekawa, Yasuo

doi:10.1109/mm.2011.95

Cited by 17 publications

(15 citation statements)

References 13 publications

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“…Most of the industrial mappings of wireless standards on SDR (Software Defined Radio) platforms, carried out for complete receivers [9], typically neither explore P&A nor analyze the trade-offs in details. Besides this, PHY layer implementations mostly focus on on efficient implementations for the computationally dominant blocks, such as MIMO detectors and FFT [7] [8].…”

Section: Related Workmentioning

confidence: 99%

“…In the codesign space, [5] [6] traditionally partitioning decisions were limited to hardware-software partitioning only, where the design space is limited. Most of the works in ASIP based MPSoC designs with P&A exploration [7][8] [9] either do not consider complete application and focus on specific parts only or carry out limited exploration. Further, the problem of P&A and architecture exploration gets amplified exponentially with applications with multiple modes (runtime profiles) [10] or even more in case of multiple applications [11].…”

Section: Introductionmentioning

confidence: 99%

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Early exploration for platform architecture instantiation with multi-mode application partitioning

Agrawal

Raghavan

Hartman

et al. 2013

Proceedings of the 50th Annual Design Automation Conference

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We present a systematic methodology for exploring application partitioning and assignment together with platform architecture instantiation. Streaming applications with multiple runtime modes are considered. The platform architecture is based on a domain specific MPSoC architecture template. We show results using complete inner modem physical layer processing of wireless applications, WLAN and LTE. We show that the proposed methodology obtains up to 30% energy improvement in energy with negligible area overheads as compared to straight-forward mapping to one processor, while meeting performance constraints, for a multi-mode WLAN 11n system and single-mode LTE system.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Early exploration for platform architecture instantiation with multi-mode application partitioning

Agrawal

Raghavan

Hartman

et al. 2013

Proceedings of the 50th Annual Design Automation Conference

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show abstract

“…The implemented chip is capable of decoding 1080p main profile H.264 video streams at 24 frames per second (fps). ADRES, which combines a VLIW processor with a reconfigurable array of 8 × 8 function units, is presented by Suzuki et al [5]. In this design, the reconfigurable array is used to accelerate the dataflow-like kernels, whereas the VLIW core executes the non-kernel code by exploiting instruction-level parallelism.…”

Section: Introductionmentioning

confidence: 99%

An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform

Liu

Wang

Chen

et al. 2016

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper presents the design of a multiple-standard 1080 high definition (HD) video decoder on a mixed-grained reconfigurable computing platform integrating coarse-grained reconfigurable processing units (RPUs) and FPGAs. The proposed RPU, including 16 × 16 multi-functional processing elements (PEs), is used to accelerate computeintensive tasks in the video decoding. A soft-core-based microprocessor array is implemented on the FPGA and adopted to speed-up the dynamic reconfiguration of the RPU. Furthermore, a mail-box-based communication scheme is utilized to improve the communication efficiency between RPUs and FPGAs. By exploiting dynamic reconfiguration of the RPUs and static reconfiguration of the FPGAs, the proposed platform achieves scalable performances and cost trade-offs to support a variety of video coding standards, including MPEG-2, AVS, H.264, and HEVC. The measured results show that the proposed platform can support H.264 1080 HD video streams at up to 57 frames per second (fps) and HEVC 1080 HD video streams at up to 52fps under 250MHz, at the same time, it achieves a 3.6× performance gain over an industrial coarse-grained reconfigurable processor for H.264 decoding, and a 6.43× performance boosts over a general purpose processor based implementation for HEVC decoding.

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“…Some recent studies [15][16][17][18] show that further exploiting instruction level parallelism (ILP) out of ADRES architecture can cause hardware and software (compiler) inefficiency. This is mainly because ADRES utilizes heavily ported global register file and multi-degree point-to-point connections [18].…”

Section: Introduction and Related Workmentioning

confidence: 99%

“…Using integer linear programming to find better code schedule may incur prohibitive long runtime [16]. Given the difficulty of further pushing for ILP performance, [17] turned to exploit thread-level parallelism in MT-ADRES.…”

Section: Introduction and Related Workmentioning

confidence: 99%

A Coarse-Grained Reconfigurable Architecture with Compilation for High Performance

Wan

Dong

Chen

2012

International Journal of Reconfigurable Computing

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We propose afast data relay(FDR) mechanism to enhance existing CGRA (coarse-grained reconfigurable architecture). FDR can not only provide multicycle data transmission in concurrent with computations but also convert resource-demanding inter-processing-element global data accesses into local data accesses to avoid communication congestion. We also propose the supporting compiler techniques that can efficiently utilize the FDR feature to achieve higher performance for a variety of applications. Our results on FDR-based CGRA are compared with two other works in this field: ADRES and RCP. Experimental results for various multimedia applications show that FDR combined with the new compiler deliver up to 29% and 21% higher performance than ADRES and RCP, respectively.

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High-Throughput, Low-Power Software-Defined Radio Using Reconfigurable Processors

Cited by 17 publications

References 13 publications

Early exploration for platform architecture instantiation with multi-mode application partitioning

Early exploration for platform architecture instantiation with multi-mode application partitioning

An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform

A Coarse-Grained Reconfigurable Architecture with Compilation for High Performance

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