2018
DOI: 10.1109/tvlsi.2018.2809644
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High-Throughput Pattern Matching With CMOL FPGA Circuits: Case for Logic-in-Memory Computing

Abstract: In this paper, we propose a novel CMOS+ MOLecular (CMOL) field-programmable gate array (FPGA) circuit architecture to perform massively parallel, high-throughput computations, which is especially useful for pattern matching tasks and multidimensional associative searches. In the new architecture, patterns are stored as resistive states of emerging nonvolatile memory nanodevices, while the analyzed data are streamed via CMOS subsystem. The main improvements over prior work offered by the proposed circuits are i… Show more

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Cited by 21 publications
(8 citation statements)
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“…31, has been shown to give high densities of connections, which could be useful here. 32,33 Building one physical system capable of implementing any graph problem is unrealistic. However, it would be possible to have specialized chips for types of graph problems.…”
Section: Outlook For a Reconfigurable Graph Solvermentioning
confidence: 99%
“…31, has been shown to give high densities of connections, which could be useful here. 32,33 Building one physical system capable of implementing any graph problem is unrealistic. However, it would be possible to have specialized chips for types of graph problems.…”
Section: Outlook For a Reconfigurable Graph Solvermentioning
confidence: 99%
“…Additional parasitics in the time delay network, such the capacitance of the memristor, would increase the energy cost of producing delays while also affecting the range of achievable delays. However, typical memristor parasitic capacitances are a fraction of the gate capacitances used in this study [58,59] and we estimate that the achievable delays per RC block of the time delay network decrease by less than fifteen percent. Such reductions in the achievable delay ranges could be readily compensated by the addition of additional delay blocks or by allowing a larger resistance values for each memristor.…”
Section: Circuits For Complex Synaptic Weightsmentioning
confidence: 87%
“…There are various challenges in 3D passive array designing, such as the sneaking current, disturbance, IR drop, thermal coupling, etc, which greatly retard the progress towards commercialization. Apart from data storage, the passive network also has other potential applications, such as neuromorphic computing, [23] 3D CMOS/molecular circuits (CMOL), [24] etc., with promising prospect of low cost and high energy efficiency. In this review article, we will firstly address the associative problems in passive array and 3D architectures (Section 2), and then review the states of the art of various selector devices and selfselective cells (Section 3).…”
Section: Introductionmentioning
confidence: 99%