High-Voltage 3-D Partial SOI Technology Platform for Power Integrated Circuits

Abstract

Partial SOI (PSOI) is a widely recognized technology suitable for High Voltage (HV) architectures for Power Integrated Circuits (PICs). Despite the added process complexity compared to SOI RESURF, this technology offers a wider range of voltage ratings due to the action of the depletion layer in the Handle Wafer (HW), reduced parasitic capacitances due to the extra volume of the depletion region in the HW and better heat conduction due to thinner buried oxide layer. The newly developed platform technology, featuring 3-dimensional designs to fully utilize the PSOI potential, is particularly relevant to the manufacturing of high voltage integrated circuits (HVICs) where low on-state resistance and reduced selfheating are essential requirements. This work presents a PSOI technology platform with voltage ratings ranging from 45 to 400V while providing low on-state resistance, good hot carrier injection stability as well as Electrostatic Discharge (ESD) capability of the HV devices. For example, for a 375V rated LDMOSFET, this technology achieves an on-state resistance of 1435mΩ.mm 2 , an over 50% improvement compared to the state-of-the-art SOI technologies while maintaining competitive reliability.

Novel Constant Surface Concentration Depletion Mechanism and Its Experiments in Homogenization field LDMOS

“…Fig. 8 Ron,sp-VB characteristics of the CSD HOF LDMOS and reported experiments [3]- [8], [14]- [15]. The CSD HOF LDMOS realizes a Ron,sp reduced by 20.8% when compared with the HOF LDMOS we reported in [14].…”

“…Then, the surface doping concentration Ns of the device decreases with an increase in the depth of the doping junction. The different constant doping doses has also been discussed by both analytical models and experiments [8]- [11]. This phenomenon is referred to as constant dose depletion in this paper.…”

A 110/230 V AC and 15–400 V DC 0.3 W Power-Supply IC With Integrated Active Zero-Crossing Buffer

“…The converter has been implemented in a 0.18 μm HV CMOS partial-SOI technology [17], [18]. It uses a reverse-biased junction depleting the handle wafer under the HV devices to achieve both high breakdown voltages and small devices at the same time [19].…”