High‐voltage EDMOS transistor with dual work function gate

Abstract

A high-voltage extended drain MOS (EDMOS) transistor with a dual work function gate (DWFG) is discussed. This device enhances device performance by modifying the electric field in the channel. For DWFG EDMOS device fabrication, the polycrystalline silicon gates on the source and drain sides are doped by p + and n + ion implantation, respectively. Experimental results from the fabricated DWFG EDMOS devices show improved transconductance (g m), drain conductance (g ds) and specific on-resistance (R ON) characteristics without breakdown voltage reduction.

Performance Optimization of LDMOS Transistor with Dual Gate Oxide for Mixed-Signal Applications

“…Recently, several groups have proposed a range of LDMOS structures to improve their device performance [5][6][7][8][9][10][11][12][13][14]. In advanced reduced surface field (RESURF) technologies and fieldplate gate structures, attention has been paid to the reduced device size and on-resistance (R ON ) while maintaining the breakdown voltage (BV) [5].…”

“…These techniques are effective only for the switching characteristics of power ICs. Alternatively, some LDMOS devices using gate and channel engineering have been reported [6][7][8][9][10][11][12]. These LDMOS devices are based on the splitgate field-effect transistor (SGFET) concept [13].…”

“…The modulated channel potential due to the asymmetric channel resistance can improve the device performance. One of the imple-mentations of LDMOS devices through gate engineering showed improved device performance for mixed-signal applications [6][7][8][9]. Another LDMOS device with a lateral asymmetric channel (LAC) was also shown to improve the electrical characteristics [10][11][12].…”