High volume microprocessor test escapes, an analysis of defects our tests are missing

Needham, W.; Prunty, C.; Yeoh, Eng Hong

doi:10.1109/test.1998.743133

Cited by 168 publications

(90 citation statements)

References 5 publications

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“…An important sub-category of these defects are temperature-sensitive defects [Needham98]. For example, some defects show up only when the IC follows a certain temperature pattern [Hagihara97].…”

Section: Temperature Dependent Defectsmentioning

confidence: 99%

“…An example for such temperature-sensitive defect is a resistive open which is a major cause of test escapes [Needham98]. It occurs when a connection between two circuit nodes has a conductance high enough to be considered connected at normal temperatures.…”

Section: Temperature Dependent Defectsmentioning

confidence: 99%

“…On the other hand, we have other defects that manifest themselves differently with respect to temperature. For example, in [Needham98] a defect ("Dark Via") is reported that "had previously passed all production tests, but then failed a monitor test at cold temperature". Several other defects are also identified in [Needham98] that similarly appear only at low temperatures.…”

Section: Temperature Dependent Defectsmentioning

confidence: 99%

“…The Dark Via defect, which appears at low temperature, could be seen as voids between interconnect and via [Needham98,Segura04]. This observation could be explained with thermal expansion in metals that fills up the voids and increases the conductivity.…”

Section: Temperature Dependent Defectsmentioning

confidence: 99%

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Thermal Issues in Testing of Advanced Systems on Chip

Ghaleshahi¹

2015

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Many cutting-edge computer and electronic products are powered by advanced Systems-on-Chip (SoC). Advanced SoCs encompass superb performance together with large number of functions. This is achieved by efficient integration of huge number of transistors. Such very large scale integration is enabled by a core-based design paradigm as well as deepsubmicron and 3D-stacked-IC technologies. These technologies are susceptible to reliability and testing complications caused by thermal issues. Three crucial thermal issues related to temperature variations, temperature gradients, and temperature cycling are addressed in this thesis.Existing test scheduling techniques rely on temperature simulations to generate schedules that meet thermal constraints such as overheating prevention. The difference between the simulated temperatures and the actual temperatures is called temperature error. This error, for past technologies, is negligible. However, advanced SoCs experience large errors due to large process variations. Such large errors have costly consequences, such as overheating, and must be taken care of. This thesis presents an adaptive approach to generate test schedules that handle such temperature errors.Advanced SoCs manufactured as 3D-stacked-ICs experience large temperature gradients. Temperature gradients accelerate certain early-life defect mechanisms. These mechanisms can be accelerated using gradientbased, burn-in like operations so that the defects are detected before shipping. Moreover, temperature gradients exacerbate some delay-related defects. In order to detect such defects, testing must be performed when appropriate temperature-gradients are enforced. Schedule-based techniques that enforces the temperature-gradients for burn-in like operations and delay testing are proposed in this thesis. Abstract iiThe last thermal issue addressed by this thesis is related to temperature cycling. Temperature cycling test procedures are usually applied to safetycritical systems to detect cycling-related early-life failures. Such failures affect advanced SoCs, particularly through-silicon-via structures in 3D-stacked-ICs. An efficient schedule-based cycling-test technique that combines cycling acceleration with testing is proposed in this thesis. The proposed technique fits into existing 3D testing procedures and does not require temperature chambers. Therefore, the overall cycling acceleration and testing cost can be drastically reduced.All the proposed techniques have been implemented and evaluated with extensive experiments based on ITC'02 benchmarks as well as a number of 3D stacked ICs. Experiments show that the proposed techniques work effectively and reduce the test costs. We have also developed a fast temperature simulation technique based on a closed-form solution for the temperature equations. Experiments demonstrate that the proposed simulation technique reduces the test schedule generation time by more than half.iii Populärvetenskaplig sammanfattningMånga banbrytande dator-och elektronikprodukter drivs...

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Section: Temperature Dependent Defectsmentioning

confidence: 99%

Section: Temperature Dependent Defectsmentioning

confidence: 99%

Section: Temperature Dependent Defectsmentioning

confidence: 99%

Section: Temperature Dependent Defectsmentioning

confidence: 99%

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Thermal Issues in Testing of Advanced Systems on Chip

Ghaleshahi¹

2015

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“…In particular in [16] Intel reports that open/resistive vias are the most common root cause of test escapes in deepsubmicron technologies.…”

Section: Introductionmentioning

confidence: 99%

Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test

Borri¹,

Hage-Hassan²,

Dilillo

et al. 2005

J Electron Test

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Abstract. This paper presents the results of resistive-open defect insertion in different locations of Infineon 0.13 µm embedded-SRAM with the main purpose of verifying the presence of dynamic faults. This study is based on the injection of resistive defects as their presence in VDSM technologies is more and more frequent. Electrical simulations have been performed to evaluate the effects of those defects in terms of detected functional faults. Read destructive, deceptive read destructive and dynamic read destructive faults have been reproduced and accurately characterized. The dependence of the fault detection has been put in relation with memory operating conditions, resistance value and clock cycle, and the importance of at speed testing for dynamic fault models has been pointed out. Finally resistive Address Decoder Open Faults (ADOF) have been simulated and the conditions that maximize the fault detection have been discussed as well as the resulting implications for memory test.

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The Reliability Toolbox

Levin

Kalal

2003

Improving Product Reliability

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High volume microprocessor test escapes, an analysis of defects our tests are missing

Cited by 168 publications

References 5 publications

Thermal Issues in Testing of Advanced Systems on Chip

Thermal Issues in Testing of Advanced Systems on Chip

Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test

The Reliability Toolbox

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