Highly Flexible and High‐Performance Complementary Inverters of Large‐Area Transition Metal Dichalcogenide Monolayers

Pu, Jiang; Funahashi, Kazuma; Chen, Chang-Hsiao; Li, Mingyang; Li, Lain‐Jong; Takenobu, Taishi

doi:10.1002/adma.201503872

Cited by 123 publications

(126 citation statements)

References 58 publications

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“…Figure S9 (Supporting Information) shows the phase angle becomes almost −85°, and the calculated capacitance is approximately constant during the frequency <10 3 Hz. The C i of each InSe device was measured in the range of 5–7 µF cm −2 , which is reasonably close to that of previous report in TMDs (5–10 µF cm −2 ) . Based on the measured specific capacitance, the gate voltage dependence of calculated carrier mobilities is plotted as shown in Figure e.…”

Section: Resultssupporting

confidence: 84%

Synthesis of Large‐Area InSe Monolayers by Chemical Vapor Deposition

Chang

Lin

et al. 2018

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Recently, 2D materials of indium selenide (InSe) layers have attracted much attention from the scientific community due to their high mobility transport and fascinating physical properties. To date, reports on the synthesis of high-quality and scalable InSe atomic films are limited. Here, a synthesis of InSe atomic layers by vapor phase selenization of In O in a chemical vapor deposition (CVD) system, resulting in large-area monolayer flakes or thin films, is reported. The atomic films are continuous and uniform over a large area of 1 × 1 cm , comprising of primarily InSe monolayers. Spectroscopic and microscopic measurements reveal the highly crystalline nature of the synthesized InSe monolayers. The ion-gel-gated field-effect transistors based on CVD InSe monolayers exhibit n-type channel behaviors, where the field effect electron mobility values can be up to ≈30 cm V s along with an on/off current ratio, of >10 at room temperature. In addition, the graphene can serve as a protection layer to prevent the oxidation between InSe and the ambient environment. Meanwhile, the synthesized InSe films can be transferred to arbitrary substrates, enabling the possibility of reassembly of various 2D materials into vertically stacked heterostructures, prompting research efforts to probe its characteristics and applications.

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Section: Resultssupporting

confidence: 84%

Synthesis of Large‐Area InSe Monolayers by Chemical Vapor Deposition

Chang

Lin

et al. 2018

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“…

to construct complementary metal oxide semiconductors (CMOS). [12] Since the demonstration of the vapor phase growth of small MoS 2 ML flakes, [13] significant progress has been made including the growth of large-flake, [14,15] wafer-scale, [16,17] and even roll-to roll [18] ML TMDs. Chemical or physical [10,11] doping may transform one type of TMD to the other, but the associated defects and poor thermal stability make such doping processes unrealistic for practical applications.

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confidence: 99%

Metal‐Guided Selective Growth of 2D Materials: Demonstration of a Bottom‐Up CMOS Inverter

et al. 2019

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to construct complementary metal oxide semiconductors (CMOS). Ion implantation has been widely adopted for tuning the channel polarity in Si-semiconductors; however, it causes severe damage to 2D TMD materials. Chemical or physical [10,11] doping may transform one type of TMD to the other, but the associated defects and poor thermal stability make such doping processes unrealistic for practical applications. Therefore, the concept of using two dissimilar TMDs, one p-and one n-type TMD, has been recently demonstrated for circuit applications. [12] Since the demonstration of the vapor phase growth of small MoS 2 ML flakes, [13] significant progress has been made including the growth of large-flake, [14,15] wafer-scale, [16,17] and even roll-to roll [18] ML TMDs. The direct growth of seamless junctions between two dissimilar ML TMDs [19][20][21][22][23] has also been achieved. Besides, it is also demonstrated to grow two types of TMDs by conversion of two metal oxides on separate substrates. [24] These approaches, while encouraging, cannot grow two dissimilar ML TMDs on the same substrate in a highly location-selective manner. Here, we report a bottom-up growth called metal-guided selective growth (MGSG), which allows the precise deposition of specific TMDs onto desired locations controlled by the patterned metal pads. The proposed new method also enables the concurrent growth of two dissimilar ML TMDs on the same substrate; hence, well-defined lateral or vertical 2D transition metal dichalcogenide (TMD) layered materials are promising for future electronic and optoelectronic applications. The realization of large-area electronics and circuits strongly relies on wafer-scale, selective growth of quality 2D TMDs. Here, a scalable method, namely, metalguided selective growth (MGSG), is reported. The success of control over the transition-metal-precursor vapor pressure, the first concurrent growth of two dissimilar monolayer TMDs, is demonstrated in conjunction with lateral or vertical TMD heterojunctions at precisely desired locations over the entire wafer in a single chemical vapor deposition (VCD) process. Owing to the location selectivity, MGSG allows the growth of p-and n-type TMDs with spatial homogeneity and uniform electrical performance for circuit applications. As a demonstration, the first bottom-up complementary metaloxide-semiconductor inverter based on p-type WSe 2 and n-type MoSe 2 is achieved, which exhibits a high and reproducible voltage gain of 23 with little dependence on position. 2D MaterialsTransition metal dichalcogenides (TMDs) such as MoS 2 have been recognized as high on-off ratio semiconductors [1] which are promising for high-quantum yield optoelectronics, [2] next-generation transistors, [3] and integrated circuit (IC) applications. [4,5] In addition to the use of a single MoS 2 material, the formation of p-n junctions between two different TMD monolayers (MLs) enables device functionalities including current rectifying, light emitting, and photon harvesting. [6][7][8][9]

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“…[15] On the other hand, large hysteresis caused, for example, by charge traps [2] and significant Schottky barriers [16] at the metal-semiconductor interface are still a major design challenge for the realization of novel device architectures. They have been shown to cause degradation in the performance of transistors [17] and generate high levels of flicker noise. [18,19] To overcome these challenges, hysteresis is usually avoided by encapsulation [20,21] or operation under high vacuum.…”

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confidence: 99%

Role of Charge Traps in the Performance of Atomically Thin Transistors

et al. 2017

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The emerging family of atomically thin materials is fueling the development of conceptually new technologies [1] in highly efficient optoelectronics [2,3] and photonic applications, [4] to name a few. The large variety of bandgap values found in layered transition-metal dichalcogenides (TMDCs) [5,6] make these materials especially suited for transistor applications. TMDCs are compounds with the general formula MX 2 , where M is a transition metal, e.g., Mo and W, and X is an element of the chalcogen group, S, Se, and Te. They appear in a layered structure where the metal forms a hexagonal plane and the chalcogenides are positioned over and under this plane in either a trigonal prismatic (2H), as shown in Figure 1a, or octahedral (1T) stacking configuration. [7] In the semiconducting 2H systems, the compounds show a transition from indirect bandgap in bulk materials to direct bandgap in single layers. [8] Transient currents in atomically thin MoTe 2 field-effect transistors (FETs) are measured during cycles of pulses through the gate electrode. The curves of the transient currents are analyzed in light of a newly proposed model for charge-trapping dynamics that renders a time-dependent change in the threshold voltage as the dominant effect on the channel hysteretic behavior over emission currents from the charge traps. The proposed model is expected to be instrumental in understanding the fundamental physics that governs the performance of atomically thin FETs and is applicable to the entire class of atomically thin-based devices. Hence, the model is vital to the intelligent design of fast and highly efficient optoelectronic devices.Single-and few-layered TMDCs have been implemented in a wide range of applications, ranging from thin film transistors, [9] digital electronics and optoelectronics, [2,10,11] flexible electronics, [12] and up to energy conversion and storage devices. [13] However, the defect states in TMDCs have an ambivalent nature and can have a major positive or negative impact on the performance of atomically thin devices. The presence of defects in photodetectors can be beneficial since it has been shown to immobilize charges at the channel which improves the gain in photodetectors [14] and produces nonvolatile memory mechanisms. [15] On the other hand, large hysteresis caused, for example, by charge traps [2] and significant Schottky barriers [16] at the metal-semiconductor interface are still a major design challenge for the realization of novel device architectures. They have been shown to cause degradation in the performance of transistors [17] and generate high levels of flicker noise. [18,19] To overcome these challenges, hysteresis is usually avoided by encapsulation [20,21] or operation under high vacuum. [22,23] Most of the current research into surface states of TMDCs has focused on the chemical origins of charge trapping. A full understanding of their effect on the electrical properties is still lacking, hindering the optimization of functional components. While hysteresis has been sho...

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Highly Flexible and High‐Performance Complementary Inverters of Large‐Area Transition Metal Dichalcogenide Monolayers

Cited by 123 publications

References 58 publications

Synthesis of Large‐Area InSe Monolayers by Chemical Vapor Deposition

Synthesis of Large‐Area InSe Monolayers by Chemical Vapor Deposition

Metal‐Guided Selective Growth of 2D Materials: Demonstration of a Bottom‐Up CMOS Inverter

Role of Charge Traps in the Performance of Atomically Thin Transistors

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