Highly linear CMOS power amplifier for mm-wave applications

Park, Byungjoon; Jeong, Daechul; Kim, Jooseung; Cho, Yunsung; Moon, Kibong; Kim, Bumman

doi:10.1109/mwsym.2016.7540024

Cited by 28 publications

(6 citation statements)

References 4 publications

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“…Figure 9. Two stage CMOS power amplifier [15] In 2016, [16] proposed one-stage differential structure having a harmonic control circuit to minimize the 2nd harmonics produced by the non-linear CS amplifier at the drain and source as shown in Figure 10. By short circuit the drain and source, 2nd harmonic issue can be reduced as it will be trap at drain and source.…”

Section: Ka Band Design Techniquementioning

confidence: 99%

“…Figure 10. One-stage differential structure CMOS power amplifier with a harmonic control circuit [16] Later, [17] proposed a small inter-stage inductor between the cascode common-source and commongate to improve PA's output power and PAE as shown in Figure 11. The input balun separates the singleended RF signal into a pair of differential signals, and then these signals are amplified through two-stage cascodeamplifiers, in the end the output balun merges the differential signals for a higher output power.…”

Section: Ka Band Design Techniquementioning

confidence: 99%

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Study of CMOS power amplifier design techniques for ka-band applications

Hasan¹,

Murad²,

Rani³

et al. 2019

IJEECS

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<span>This paper reviews of high efficiency CMOS power amplifiers (PAs) in millimeter (mm) wave Ka - Band applications. The study is focused on the challenges in designing PA especially in GHz frequencies inclusive of high gain, good input and output matching, efficiency, linearity, low group delay and low power consumption. Several works on CMOS PA from year 2009 to 2018 are discussed in this paper. Recent developments of CMOS PAs are examined and a comparison of the performance criteria of various techniques is presented.</span>

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Section: Ka Band Design Techniquementioning

confidence: 99%

Section: Ka Band Design Techniquementioning

confidence: 99%

Study of CMOS power amplifier design techniques for ka-band applications

Hasan¹,

Murad²,

Rani³

et al. 2019

IJEECS

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“…Four dominant IMD3 contributors are present in a CMOS PA: 1) the 3rd-order transconductance (g m3 ); 2) the gain compression due to drain voltage clipping; 3) the voltage-dependent nonlinear parasitic capacitors (e.g., gate-source C gs , gate-drain C gd , and gate-bulk C gb ); and 4) the 2nd-order mixing products. Enhanced 2nd-harmonic termination [2], [3], pMOS varactor-based amplitude-to-phase (AM-PM) compensation [4], [5], hybrid nMOS/pMOS PA structures [6]- [8], and transformer-based AM-PM correction [9] are proposed to improve the mm-wave PAs' linearity, deteriorated by the 2nd-order mixing products and nonlinear capacitors. Moreover, adaptive biasing, multi-gate transistor, and antiphase [10]- [18] techniques are proposed for IMD3 cancellation.…”

Section: Introductionmentioning

confidence: 99%

Load-Modulation-Based IMD3 Cancellation for Millimeter-Wave Class-B CMOS Power Amplifiers Achieving EVM < 1.2%

Pashaeifar

Vreede

Alavi

2022

IEEE Microw. Wireless Compon. Lett.

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This letter presents a novel load-modulation-based 3rd-order intermodulation distortion (IMD3) cancellation technique for class-B CMOS power amplifiers (PAs). In a class-B PA, the IMD3 generated by the 3rd-order transconductance (g m3 ) and the gain compression have opposite signs, and thus, they can cancel each other at specific bias and loading conditions. The proposed Doherty topology allows adjusting the gain compression by modulating the effective loading, facilitating IMD3 cancellation over the entire load modulation region. The proposed approach is verified using a 28 GHz 40 nm CMOS series-Doherty PA (DPA) topology. The experimental result demonstrates 10/17 dB IMD3 improvement compared to class-B/DPA operation. Without using any digital pre-distortion, the measured EVM of the proposed technique for a 50 MHz 64-QAM OFDM signal with 8.9 dBm average output power is −38.7 dB (1.2%), which is 5.7/11 dB better than a standard class-B/DPA operation.

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“…In the midst of the pervasive growth of the fifth generation (5G) millimeter-wave technology, the design of millimeter-wave (mm-wave) systems become challenging as the demand of broadband data traffic increased [1]. Efficiency of the transceiver is required in mm-wave systems and the sub block of the transceiver which is power amplifiers play significant performance in transmitters due to extensive power consumption [2][3][4]. As CMOS technology offer low cost and high integration level for manufacturing volume, it does attract the design for transceiver system [5,6].…”

Section: Introductionmentioning

confidence: 99%

A 28 GHz high efficiency fully integrated 0.18 µm combined CMOS power amplifier using power divider technique for 5G millimeter-wave applications

Hasan¹,

Murad²,

Bakar³

et al. 2020

Bulletin EEI

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A 28 GHz power amplifier (PA) using CMOS 0.18 µm Silterra process technology for milimeter wave applications is reported. Maximizing the power added efficiency (PAE) and output power are achieved by optimize the circuit with power divider and cascade configuration. In addition, reverse body bias is also employed for realizing excellent PAE and power consumption. A three stage CMOS PA with power combiner is designed and simulated. The simulation results show that the proposed PA consumes 62.56 mW and power gain (S21) of 8.08 dB is achieved at 28 GHz. The PA achieves saturated power (Psat) of 12.62 dBm and maximum PAE of 23.74% with output 1-dB compression point (OP1dB) 10.85 dBm. These results demonstrate the proposed power amplifier architecture is suitable for 5G applications.

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Highly linear CMOS power amplifier for mm-wave applications

Cited by 28 publications

References 4 publications

Study of CMOS power amplifier design techniques for ka-band applications

Study of CMOS power amplifier design techniques for ka-band applications

Load-Modulation-Based IMD3 Cancellation for Millimeter-Wave Class-B CMOS Power Amplifiers Achieving EVM < 1.2%

A 28 GHz high efficiency fully integrated 0.18 µm combined CMOS power amplifier using power divider technique for 5G millimeter-wave applications

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