Highly manufacturable silicon vertical diode switches for new memories using selective epitaxial growth with batch-type equipment

Abstract

Practical selectivity window of selective epitaxial growth (SEG) using a H 2 /SiH 4 /Cl 2 cyclic chemical vapor deposition (CVD) system has been investigated with the batch-type vertical furnace equipment, replacing a conventional single-wafer H 2 /dichlorosilane/HCl CVD system. The process temperature was less than 700 • C, which is suitable for a low thermal budget process applicable to next-generation memories including vertical pn-diode switches. Selectivity loss is quantified by an in-line inspection tool to determine the practical number of selectivity losses. The H 2 /SiH 4 /Cl 2 cyclic CVD system provides an excellent capacity of 40 wafers per batch. Selectivity loss, which is one of the most crucial features in the SEG process for the diode application, is controlled with both the amount of SiH 4 and Cl 2 and the period of gas supply, and the practical number of selectivity loss is confirmed to be less than 100 in 200 mm wafers. Without high temperature annealing in hydrogen ambient, low temperature cyclic SEG in the batch reactor ensures the clean interface and improved crystalline quality of SEG-Si, as well as high throughput.

The Enhancement of Etch Rate of Silicon by Heavy Doping of Phosphorus and Arsenic Atoms During Cyclic Selective Epitaxial Growth of Silicon

“…Due to the low throughput of single-type SEG equipment, the batchtype SEG process has been investigated for the memory application. We also have reported the characteristics of SEG process using batch-type equipment [4,5], where a cyclic SEG process was realized by the alternative supply of SiH 4 and Cl 2 gases. In this study, we speculate the mechanism of the micro-void formation at the interface between SEG and substrate silicon by means of the process window of the cyclic SEG scheme.…”

“…In this study, we speculate the mechanism of the micro-void formation at the interface between SEG and substrate silicon by means of the process window of the cyclic SEG scheme. Process flows of the experiment are available elsewhere [4,5]. shows the cross-section of diodes after 10 cycles of SEG process.…”