Highly reliable 0.15 μm MOSFETs with Surface Proximity Gettering (SPG) and nitrided oxide spacer using nitrogen implantation

Kuroi, T.; Shimizu, Satoshi; Furukawa, Akira; Komori, S.; Kawasaki, Yoji; Kusunoki, S.; Okumura, Y.; Inuishi, N. Mikoshiba Y.; Tsubouchi, Nobuteru; Horie, Kazuma

doi:10.1109/vlsit.1995.520839

Cited by 10 publications

(8 citation statements)

References 1 publication

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“…[1][2][3] Nitrogen was proposed to be co-implanted into BF + 2 -implanted p +poly-Si gate to suppress the boron penetration, 1) or into the source-drain region to improve the junction leakage, 2) or into the channel region to improve the n-channel device performance. 3) Meanwhile, N 2 O oxide has also been proposed as a promising gate oxide material for deep sub-micron devices.…”

Section: Introductionmentioning

confidence: 99%

THE KORTEWEG-DE VRIES EQUATION IN CLASSES OF INCREASING FUNCTIONS WITH PRESCRIBED ASYMPTOTICS AS $ \vert x\vert\to\infty$

Bondareva¹

1985

Math. USSR Sb.

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The combined effects of N 2 -implantation at S/D extension and N 2 O oxide on 0.18 µm n-and p-Metal oxide field effect transistors (MOSFETs) were investigated. It is found that for n-channel transistors, V th roll-off and drain-induced barrier lowering (DIBL) are enhanced by nitrogen incorporation through either N 2 O oxide or N 2 -implantation. However, for p-channel transistors, opposite trends are observed for N 2 O oxide and N 2 -implantation. Finally, nitrogen incorporation by either method is found to improve the interface quality for nMOSFETs. While for p-channel transistors, best results are obtained by the combined effects of N 2 O oxide and N 2 -implantation.

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Section: Introductionmentioning

confidence: 99%

THE KORTEWEG-DE VRIES EQUATION IN CLASSES OF INCREASING FUNCTIONS WITH PRESCRIBED ASYMPTOTICS AS $ \vert x\vert\to\infty$

Bondareva¹

1985

Math. USSR Sb.

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“…The implanted nitrogen atoms in the poly-Si gate are segregated at the oxide-silicon interface by the annealing, as shown in Fig.6. In the ultra-shallow doping, the lowered annealing temperature causes insufficient recovery from the implant damage, and abnormal leakage current used to be observed as shown in Fig.7 13) . The V th instability caused by the hot carrier trapping at the interface can be greatly improved.…”

Section: Nm Cmos Process With Full Utilization Of Ion Implantationmentioning

confidence: 99%

Evolution of Ion Implantation Technology and its Contribution to Semiconductor Industry

Tsukamoto¹,

Kuroi²,

Kawasaki³

et al. 2011

AIP Conference Proceedings

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Industrial aspects of the evolution of ion implantation technology will be reviewed, and their impact on the semiconductor industry will be discussed. The main topics will be the technology's application to the most advanced, ultra scaled CMOS, and to power devices, as well as productivity improvements in implantation technology. Technological insights into future developments in ion-related technologies for emerging industries will also be presented.

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“…Second, hot carrier injection (HCI) degradation for I/O transistors is most concerning part when shrink [6]. It can be improved that thick transistor (3.3V MOS) using additional liner oxide before LDD implant and the optimization of LDD implant.…”

Section: ⅰ Introductionmentioning

confidence: 99%

A Study on the DC parameter matching according to the shrink of 0.13㎛ technology

Mun¹,

Kang²,

Joung³

2014

The Journal of the Korea institute of electronic communication

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본 논문은 기존의 poly length만의 축소와 달리 입, 출력 소자를 포함한 core 디바이스의 0.13㎛ 디자인을 10% 축소하는 것으로 여러 채널 길이에 따른 body effect와 doping profile simulation을 해석하였다. 축소 전 의 DC 파라미터 매칭을 위하여 게이트 산화막의 decoupled plasma nitridation 처리와 LDD(Lightly Doped Drain) 이온주입 전 TEOS(Tetraethylortho silicate) 산화막 100Å 그리고 LDD 이온주입을 22o tilt-angle(45o twist-angle)로 최적화하였고 그 결과 축소 전의 5%의 범위에서 매칭됨을 확인하였다.ABSTRACT This paper relates 10% shrink from 0.13㎛ design for core devices as well as input and output (I/O) devices different from previous poly length shrink size only. We analyzed body effect with different channel length and doping profile simulation. After fixing the gate oxide module process, LDD implant conditions were optimized such as decoupled plasma nitridation of gate oxide, TEOS oxide 100Å before LDD implant and 22o tilt-angle(45o twist-angle) LDD implant respectively to match the spice DC parameters of pre-shrink and finally matched them within 5%.

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Highly reliable 0.15 μm MOSFETs with Surface Proximity Gettering (SPG) and nitrided oxide spacer using nitrogen implantation

Cited by 10 publications

References 1 publication

THE KORTEWEG-DE VRIES EQUATION IN CLASSES OF INCREASING FUNCTIONS WITH PRESCRIBED ASYMPTOTICS AS $ \vert x\vert\to\infty$

THE KORTEWEG-DE VRIES EQUATION IN CLASSES OF INCREASING FUNCTIONS WITH PRESCRIBED ASYMPTOTICS AS $ \vert x\vert\to\infty$

Evolution of Ion Implantation Technology and its Contribution to Semiconductor Industry

A Study on the DC parameter matching according to the shrink of 0.13㎛ technology

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