Highly robust self-compliant and nonlinear TaO<inf>X</inf>/HfO<inf>X</inf> RRAM for 3D vertical structure in 1TnR architecture

Abstract

IntroductionOwing to NAND flash technology facing its scaling limit, resistive random access memory (RRAM) with simple film stack and no cross coupling issue between cells is a promising candidate for future high density memory application [1,2]. The 1TnR architecture with 3D vertical RRAM (VRRAM) structure realizes ultra-low bit cost for high compact density array [3,4]. However, this novel 1TnR structure and processes have not been proved yet. To meet requirements of VRRAM array operation, the nonlinear resistive memory with an excellent self-compliance and low current operation is indispensable [5,6]. A large voltage margin for the device operated with compliance current (ΔV COMP ) and high nonlinearity for the device at low resistance state (LRS) with reliable read voltage should be addressed.In this work, the key processes and the resistive switching for the VRRAM device in the 1TnR architecture are firstly demonstrated. Moreover, the TaO X /HfO X (TH) device with 1 μA operation current exhibits a large ΔV COMP (~ 1.6 V) for reliable pulse mode operation. Besides, a high LRS nonlinearity ~ 40, which can provide enough read/write margins in the VRRAM array for robust operation, is extracted from the reliable read voltage based on the constant voltage stress (CVS) test.VRRAM in 1TnR architecture Figure 1 shows the key process flow for the VRRAM device in the 1TnR architecture. Firstly, the via hole of oxide/metal multilayers were defined and etched to form the horizontal electrodes (HE) with a thickness of 40 nm, as shown in Fig. 1(a). Then, the Ta and HfO X films, respectively grown with PVD and ALD methods, and a thin TiN protection metal layer were conformally deposited, as depicted in Fig. 1(b). To open the connected hole above the bottom access transistor, the etch-back process was adopt to remove the Ta/HfO X film above the transistor via, as shown in Fig. 1(c). The HfO X VRRAM devices can keep damage-free by the protection of TiN layer during the etch-back process. Finally, as presented in Fig.1 (d), the vertical electrode (VE) was formed by the TiN metal filling the hole with the subsequent CVD process. Figure 2 demonstrates the cross-section TEM image of four VRRAM devices within the 1TnR architecture.In Fig. 3, it shows the distributions of forming voltage (V F ) for the HfO X VRRAM. Also, there is no obvious difference for the V F of the top and bottom vertical devices. The V F is larger than 5V due to small area HE (~0.018 μm 2 ), which fits well with the dependence of V F for the Ta/HfO X device on the cell size based on oxide breakdown theory [7], as shown in the inset of Fig. 3. These results prove the process stability for the initial behavior of VRRAM devices during forming in the 1TnR architecture. As shown in Fig. 4, the HfO X VRRAM device exhibits the robust resistive switching behavior with the on/off ratio larger than 10.

A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process

“…During forming at V D = 2.8 V, the select transistor limits the maximum current passing through the STI-RRAM after the device is set to LRS. The subsequent LRS state resistance level is inverse proportional to the locally clamped current, which has been found in various TaO-based RRAM devices [ 27 , 28 ].

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Retention Model of TaO/HfO x and TaO/AlO x RRAM with Self-Rectifying Switch Characteristics

“…The 1TnR architecture with three-dimensional (3D) vertical structure helps realize ultralow bit cost for highly compact dense arrays [4–6]. Several researchers have proposed operating RRAM at low current levels by changing the resistance switching mechanism from a filamentary-type to a defect-trapping-, vacancy-modulating-, or interface-type conducting path model [7–9].…”

“…Because NAND flash technology is facing a scaling limit, vertical resistive random-access memory (VRRAM) designs with low film stacks, high manufacturing yields, and no cross-coupling problems are promising candidates for high-density memory applications [ 1 – 3 ]. The 1TnR architecture with three-dimensional (3D) vertical structure helps realize ultralow bit cost for highly compact dense arrays [ 4 – 6 ]. Several researchers have proposed operating RRAM at low current levels by changing the resistance switching mechanism from a filamentary-type to a defect-trapping-, vacancy-modulating-, or interface-type conducting path model [ 7 – 9 ].…”

“…The change of switching mechanism also indicates a different direction that might improve retention [ 11 ]. Our previous studies have shown that TaO/HfO x devices can show favorable nonlinearity values of approximately 40, endurance values exceeding 1000 cycles, and 85 °C data retention [ 6 , 7 ]. Nevertheless, to obtain stable retention at such low operating current levels is still challenging.…”