Highly scalable bulk FinFET Devices with Multi-V&lt;inf&gt;T&lt;/inf&gt; options by conductive metal gate stack tuning for the 10-nm node and beyond

Ragnarsson, Lars‐Åke; Chew, Soon Aik; Dekkers, Harold; Luque, María Toledano; Parvais, B.; Keersgieter, A. De; Devriendt, K.; Ammel, A. Van; Schram, T.; Yoshida, N.; Phatak, Anup; Han, Ke; Colombeau, B.; Brand, A.; Horiguchi, N.; Thean, Aaron

doi:10.1109/vlsit.2014.6894359

Cited by 24 publications

(15 citation statements)

References 2 publications

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“…Similar to the novel process, the novel integration is also necessary for performance and reliability improvement especially in gate engineering [162,163,164,174,175]. As an example, Simple Gate Metal Anneal (SIGMA) [171] is applied for a thin TiN layer as a work function (WF) metal for CMOS (red-marked in Figure 27a).…”

Section: Reliabilitymentioning

confidence: 99%

Miniaturization of CMOS

Radamson

Zhang

et al. 2019

Micromachines

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When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

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Section: Reliabilitymentioning

confidence: 99%

Miniaturization of CMOS

Radamson

Zhang

et al. 2019

Micromachines

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“…Ragnarsson et al applied a new ALD TiAl process to demonstrate conformal low V th bulk FinFET devices [79]. Cho et al used tert-butylimido tri-diethylamido tantalum and methane/hydrogen reactive gas mixture to obtain ALD TaC x N y films.…”

Section: Evolution Of Hkmgmentioning

confidence: 99%

The Challenges of Advanced CMOS Process from 2D to 3D

Radamson

Zhang

et al. 2017

Applied Sciences

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Abstract:The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit bricks in integrated circuits (ICs) have constantly changed during the past five decades. The driving force for such scientific and technological development is to reduce the production price, power consumption and faster carrier transport in the transistor channel. Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved. This article highlights the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and then presents how the process flow faces different technological challenges. The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future FinFETs.

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“…ii) The work function of metal gates can be tuned by using PLAD's highly directional implants to penetrate and modify the high aspect ratio structure (Fig. 9) [8].…”

Section: Challenge Of 3dmentioning

confidence: 99%