HOLMES: capturing the yield-optimized design space boundaries of analog and RF integrated circuits

2008 15th IEEE International Conference on Electronics, Circuits and Systems

et al. 2008

Abstract-A novel technique is proposed in this paper that achieves a yield optimized design from a set of optimal performance points on the Pareto front. Trade-offs among performance functions are explored through multi-objective optimization and Monte Carlo simulation is used to find the design point producing the best overall yield. One advantage of the approach presented is a reduction in the computational cost normally associated with Monte Carlo simulation. The technique offers a yield optimized robust circuit design solution with transistor level accuracy. An example using an OTA is presented to demonstrate the effectiveness of the work.

Section: Monte Carlo Analysis and Solution Selectionsupporting

confidence: 76%

Section: Design Example: Symmetrical Otamentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Yield model characterization for analog integrated circuit using Pareto-optimal surface

2008 15th IEEE International Conference on Electronics, Circuits and Systems

et al. 2008

“…The performance functions are multiplied by their respective weights given in the GA string and summed to determine a total (normalised) fitness score. This summation is shown in equation (5).…”

Section: Muti-objective Optimisationmentioning

confidence: 99%

“…With reducing transistor sizes, the impact of process variations on analogue design has become very prominent and can lead to circuit performance and yield falling below specification. This issue has led to the consideration of yield in the design process, known as design for yield (DFY) [5]. The use of hierarchical design is commonplace in the IC design world and involves breaking down a large system into its constituent building blocks.…”

Section: Introductionmentioning

confidence: 99%

A New Approach for Combining Yield and Performance in Behavioural Models for Analogue Integrated Circuits

2008 Design, Automation and Test in Europe

et al. 2008

Behavioural Performance and Variation Modelling for Hierarchical-based Analogue IC Design

2008 IEEE International Behavioral Modeling and Simulation Workshop

2008

A new approach in hierarchical optimisation is presented which is capable of optimising both the performance and yield of an analogue design. Performance and yield trade offs are analysed using a combination of multiobjective evolutionary algorithms and Monte Carlo simulations. A behavioural model that combines the performance and variation for a given circuit topology is developed which can be used to optimise the system level structure. The approach enables topdown system optimisation, not only for performance but also for yield. The model has been developed in VerilogA and tested extensively with practical designs using the Spectre simulator. A benchmark OTA circuit is used to demonstrate the behavioural model development and a 7 th order video filter has been designed to demonstrate hierarchical optimisation at the system level. The results have been verified with transistor level simulations and suggest that an accurate performance and yield prediction can be achieved with the proposed algorithm.