Hot-carrier behaviour and ron-BV trade-off optimization for p-channel LDMOS transistors in a 180 nm HV-CMOS technology

Full Understanding of Hot Electrons and Hot/Cold Holes in the Degradation of p-channel Power LDMOS Transistors

“…6) can only partially explain the experimental negative ΔRON (ad-hoc TCAD simulations were carried out to monitor this aspect). In our case, contrary to [3][4][5] where the negative ΔRON is ascribed to accumulation region, we clearly identified as dominant the role played by electrons trapping along the source-side sidewall of the STI ('c1'), where, especially at high VDS, the electrons feature the highest CEDtail (Fig. 7).…”

“…9 for VDS = -50 V and -60 V. Two HII peaks are observed, located at the left (source-side) and right (drain-side) STI corners, significantly modulated by VDS. At low VDS, electrons generated in the left HII peak are mainly drifted towards the accumulation interface by the vertical electric field [3][4][5][6][7][8], while the second HII peak at the drain side is negligible. At high VDS, a relevant contribution of electrons comes from the HII peak at the right corner of the STI.…”

“…This is even more relevant in LDMOS transistors due to the large applied drain voltage leading to the need of complex lateral structures. Recently, a few studies on HCS degradation in p-channel LDMOS have been carried out reporting experiments and static simulations [3][4][5][6][7][8]. Overall, all papers ascribe the degradation to electron interface/oxide trapping mechanisms occurring in the accumulation-drift region [3][4][5][6][7][8] along with the nearby sidewall of the shallowtrench isolation (STI) [6][7][8], causing a reduction of the on-resistance (RON) and, in some cases, gate failure [8].…”

“…Recently, a few studies on HCS degradation in p-channel LDMOS have been carried out reporting experiments and static simulations [3][4][5][6][7][8]. Overall, all papers ascribe the degradation to electron interface/oxide trapping mechanisms occurring in the accumulation-drift region [3][4][5][6][7][8] along with the nearby sidewall of the shallowtrench isolation (STI) [6][7][8], causing a reduction of the on-resistance (RON) and, in some cases, gate failure [8]. In [6], electron interface trapping is localized also in the channel region, giving rise to the reduction of the threshold voltage (VTH), whereas in [3], the channel region is interested by hole trapping inducing VTH increase.…”

A lateral DMOS with partial buried-oxide layer to achieve better RESURF effect

“…And the trade-off between the breakdown voltage (BV) and the current capability for the LDMOS is always a hot topic in the research area of power devices [1,2,3]. The buried-pwell under the n-drift region is a frequentlyused method in bulk silicon process to reduce surface field (RESURF) and achieve the trade-off between BV and current capability.…”