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In this paper, we report a combined experimental/simulation analysis of the degradation induced by hot carrier mechanisms, under ON-state stress, in silicon-based LDMOS transistors. In this regime, electrons can gain sufficient kinetic energy necessary to create interface states, hence inducing device degradation. In particular, the ON-resistance degradation in linear regime has been experimentally characterized by means of different stress conditions and temperatures. The hot-carrier stress regime has been fully reproduced in the frame of TCAD simulations by using physics-based models able to provide the degradation kinetics. A thorough investigation of the spatial interface trap distribution and its gate-bias and temperature dependences has been carried out achieving a quantitative understanding of the degradation effects in the device.

In this paper, we present an analysis of the degradation induced by hot-carrier stress in new generation power LDMOS transistors. When a relatively high drain voltage is applied during the on-state regime, high energetic and/or multiple cold electrons are recognized as the main source of degradation affecting the LDMOS lifetime: the latter is usually extrapolated at typical operating drain voltages. Hence, the extrapolation criterion is particularly critical and different models have been proposed in the past and discussed in this letter. In particular, the dependence of on-resistance degradation (ΔRON) on drain bias is investigated and a simplified extrapolation model, accounting for the saturation effects of the ΔRON at long stress times, is proposed and validated by comparison with experiments and advanced physics-based TCAD simulations, confirming the ability to accurately estimate lifetime on devices featuring short-circuited source-body contacts.

Porous silicon (PSi) is a nano-to microstructured form of silicon achieved by anodic etching of a conventional silicon wafer in acidic electrolytes. [20] Since the discovery of quantum-confinement room temperature luminescence from porous silicon, [21] nanostructured porous silicon (n-PSi) has greatly attracted the attention of researchers, who dreamed of an all-silicon photonics where electronic circuits and light emitting devices were integrated together in a silicon chip. [22] As the difficulties in increasing and stabilizing light emission of n-PSi LEDs soon became apparent, reports on the modulation of bulk-silicon properties (e.g., mechanical, thermal, electrical, optical, and biochemical) through reduction to its n-PSi form [23] have sustained porous silicon research over the following years, opening new opportunities toward unexpected applications. For instance, the thermal conductivity of n-PSi can be reduced over 3 decades with respect to that of crystalline silicon (c-Si). [23,24] The low thermal conductivity of n-PSi together with a reduced heat capacitance have enabled the fabrication of thermally induced ultrasonic transducers using n-PSi as a displacement-free (i.e., nonpiezoelectric) emitter. [25] The refractive index of n-PSi can be finely tuned from that of c-Si to that of air (almost). [26] The lower n-PSi refraction index, with respect to that of c-Si, has enabled the fabrication of label-free optical biosensors exploiting back-scattered n-PSi interferometers. [27-29] Bioresorbability of n-PSi can be tuned from hours to months in physiological conditions. [23] The tunable bioresorbability of n-PSi together with its biocompatibility and photoluminescence have enabled the preparation of drug-loaded self-reporting PSi nanoparticles for medical applications. [30,31] Among electrical properties, mobility and lifetime of charge carriers in n-PSi have been also reported to be tunable with respect to that of c-Si. [32,33] The mobility of charge carriers in n-PSi was shown to reduce down to a factor 10 6 with respect to that of bulk silicon. [32] The complex structural network of silicon nanocrystallites of n-PSi produces a strong spatial dispersion of drifting carriers over multiple paths different in length and geometry, which is responsible for the strong reduction of the mobility of both electrons and holes. [32] Recent fundamental studies on n-PSi further highlighted how the lifetime Nanomaterials hold the promise of revolutionizing electronics and, in turn, its applications, thanks to the unique properties of charge carriers traveling in structures with length scale down to a few nanometers. Here, the tremendous reduction of mobility and lifetime of charge carriers when traveling in randomly arranged nanostructured silicon crystallites, namely, nanostructured porous silicon (n-PSi), is leveraged to simultaneously improve the turn-off switching speed and reverse operation voltage of solid-state devices integrated nearby. As a proof-of-concept application, it is shown that the integration of periph...

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