Hot Carrier Degradation in Deep Sub-Micron Nitride Spacer Lightly Doped Drain N-Channel Metal-Oxide-Semiconductor Transistors

Tsai, Jai-Lin; Huang, Kai-Ye; Lai, Jinn-Horng; Gong, Jeng; Yang, Fu-Jei; Lin, Shy-Jay

doi:10.1143/jjap.41.5078

Cited by 3 publications

(1 citation statement)

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“…Type-I device deliberately deteriorated the interfacial quality by enhancing the mismatch stress due to difference of atomic size between silicon and nitride. In contrast, Type-II device relieved the interfacial stress by inserting oxide (LP-TEOS) layer as a buffer [6] [7]. This difference was confirmed by electrical characterization, such as GIDL and HC degradation of cell.…”

Section: Modementioning

confidence: 99%

DRAM reliability characterization by using dynamic operation stress in wafer burn-in mode

Kim

Choi²,

Choi³

et al.

2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual.

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Capacitor over bitline(C0B)Shallow trench isolation 65A WSixlpoly-Si/SiOz Self-aligned contact (SAC) Direct tungsten ON dielectric 0.15 pm ABSTRACT Circuit to apply the dynamic operation stress (DOS) to DRAM cell in wafer bum-in (WBI) mode is successfully implemented and contributes to characterize the reliability of DRAM in wafer level. We verify that DOS during bum-in(BI) test deteriorates data retention time microscopically, which is mainly attributed to DOSinduced hot carrier (HC) degradation of DRAM cell. In addition, the characterization result of DRAM reliability by DOS-applying method in WBI mode is a good agreement with that by dynamic operation in package hum-in (PBI) mode. [Key words: wafer burn-in, package burn-in, retention time]

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Section: Modementioning

confidence: 99%