How Preserving Circuit Design Hierarchy During FPGA Packing Leads to Better Performance

Vercruyce, Dries; Vansteenkiste, Elias; Stroobandt, Dirk

doi:10.1109/tcad.2017.2717786

Cited by 6 publications

(3 citation statements)

References 20 publications

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Section: Methodsmentioning

confidence: 99%

“…The TITAN23 designs are packed by MULTIPART [15] and are placed by VPR [12]. MULTIPART is used for packing as it enables the routing of many TITAN23 designs with the default channel width of 300 [15]. However, a few TITAN23 designs have to be omitted: routing congestion problems arise for bitcoin miner with the default channel width of 300, an error occurs for LU network and gaussianblur in VPR 7.0.7, and LU230 fails during the packing with MULTIPART.…”

Section: Methodsmentioning

confidence: 99%

“…The router is implemented in an easy to adapt FPGA CAD framework, written in Java, and is publicly available on GitHub [14]. The framework also consists of a packing (MULTIPART [15]) and placement (LIQUID [16]) tool. With the addition of CROUTE, the framework is complete.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

CRoute: A Fast High-Quality Timing-Driven Connection-Based FPGA Router

Vercruyce

Vansteenkiste

Stroobandt

2019

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

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FPGA routing is an important part of physical design as the programmable interconnection network requires the majority of the total silicon area and the connections largely contribute to delay and power. It should also occur with minimum runtime to enable efficient design exploration. In this work we elaborate on the concept of the connection-based routing principle. The algorithm is improved and a timing-driven version is introduced. The router, called CROUTE, is implemented in an easy to adapt FPGA CAD framework written in Java, which is publicly available on GitHub. Quality and runtime are compared to the state-of-the-art router in VPR 7.0.7. Benchmarking is done with the TITAN23 design suite, which consists of large heterogeneous designs targeted to a detailed representation of the Stratix IV FPGA. CROUTE gains in both the total wirelength and maximum clock frequency while reducing the routing runtime. The total wire-length reduces by 11% and the maximum clock frequency increases by 6%. These high-quality results are obtained in 3.4x less routing runtime.

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Section: Methodsmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%