How Reduced Data Precision and Degree of Parallelism Impact the Reliability of Convolutional Neural Networks on FPGAs

Libano, F.; Rech, Paolo; Neuman, Brett; Leavitt, Jennings C.; Wirthlin, Michael; Brunhaver, John

doi:10.1109/tns.2021.3050707

Cited by 34 publications

(9 citation statements)

References 26 publications

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“…Additionally, it is worth also mentioning the research contribution of [35] and [36], where the authors investigate the reliability of CNNs exploiting both the 16-bit and 8-bit integer data representation. Then, moving towards an even smaller data dimension, related works in [37] and [38] exploit reduced bitwidths.…”

Section: Related Workmentioning

confidence: 99%

Investigating data representation for efficient and reliable Convolutional Neural Networks

Ruospo

Sánchez

Traiola

et al. 2021

Microprocessors and Microsystems

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Section: Related Workmentioning

confidence: 99%

Investigating data representation for efficient and reliable Convolutional Neural Networks

Ruospo

Sánchez

Traiola

et al. 2021

Microprocessors and Microsystems

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“…In [85], it is shown that applying selective Triple Modular Redundancy (TMR) to only the most vulnerable layers can mask a high percentage of faults. In [111], [112] it is evaluated how reducing the bit-width used for data representation impacts the radiation sensitivity and failure rate. In [113], it is shown that QNNs trained with fault-aware training are more resilient to soft errors.…”

Section: Fault Injection Experiments and Frameworkmentioning

confidence: 99%

Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives

Liu

Stratigopoulos³

2023

IEEE Des. Test

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In recent years, there has been an expedited trend in embracing bold and radical innovation of computer architectures, aiming at the continuation of computing performance improvement despite the slowed-down physical device scaling. One new frontier in this field focuses on Artificial Intelligence (AI) hardware. While functionality of AI hardware still remains the main focus, testability and dependability of these new architectures need to be addressed before the mainstream adoption. This survey paper covers the state-of-the-art in research and development of dependability and testability solutions for AI hardware including digital or analog implementations of Artificial Neural Networks (ANNs) and Spiking Neural Networks (SNNs), used in accelerators and neuromorphic designs. Trends, challenges and perspectives are also discussed in this paper.

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“…To mitigate this, the authors propose a Selective TMR scheme and provide analysis of potential resultant reliability and hardware cost based on models. Similarly, Libano et al [3] explored how the reliability of NN accelerators changes with various network and accelerator parameters. They show that reliability improves with reduced data precision and increased parallelism.…”

Section: Related Workmentioning

confidence: 99%

Fault-Tolerant Neural Network Accelerators With Selective TMR

et al. 2023

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Neural networks are a popular choice to accurately perform complex classification tasks. In edge applications, neural network inference is accelerated on embedded hardware platforms, which often utilise FPGA-based architectures, due to their low-power and flexible parallelism. A significant amount of applications require resilient hardware against faults, being compliant to safety standards. In this work, we present Selective TMR, an automated tool which analyses the sensitivity of computations within neural network inference to the overall network accuracy. The tool then triplicates the most sensitive computations, which increases the functional safety of the neural network accelerator without resorting to full triple modular redundancy (TMR). As a result, this allows designers to explore trade-off between accelerator reliability and hardware cost. In some cases, we see an improvement in 24% minimum accuracy under a single stuck@ hardware fault, while increasing the overall resource footprint by 56%.

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How Reduced Data Precision and Degree of Parallelism Impact the Reliability of Convolutional Neural Networks on FPGAs

Cited by 34 publications

References 26 publications

Investigating data representation for efficient and reliable Convolutional Neural Networks

Investigating data representation for efficient and reliable Convolutional Neural Networks

Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives

Fault-Tolerant Neural Network Accelerators With Selective TMR

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