HReRAM: A Hybrid Reconfigurable Resistive Random-Access Memory

Abstract

Abstract-Passive crossbar arrays of memristors have been identified as excellent alternatives for future random-access memories. One limitation is their inability of selecting a memory cell without the interference caused by the sneak-path currents from other partially selected cells, as it results not only in unnecessary waste of energy but also in larger current requirements. The complementary resistive switch (CRS), consisting in two anti-serially connected memristors, is considered a potential solution to the sneak-path problem. However, the destructive read operation and reduced endurance of the CRS render it unattractive for the otherwise excellent candidate for next-generation crossbar-based non-volatile memories. In this paper we explore the feasibility and tradeoffs of configuring part of the CRS memory into a memristive mode to mitigate these limitations. The inherent locality of memory accesses for most computer programs offers an opportunity for designing a cache-like adaptive CRS-based crossbar memory with hybrid configurations of CRS and memristive modes, enabling optimization for both endurance and energy consumption. Our simulation results validate that the proposed hybrid system achieves 1.5-7x reduction in energy consumption in comparison with a memristive-only memory system and significantly improves the endurance of the CRS-based memory. I. INTRODUCTIONPurely memristive non-volatile crossbar arrays are potential candidates as alternatives to existing non-volatile and volatile memories. Due to its unique characteristics, a memristor can provide better-than-NAND Flash storage densities with read and write operation speeds that are comparable to DRAM [17]. A purely memristive crossbar contains no active or select elements in the memory matrix, which makes it very competitive with other emerging memory technologies as well.Purely memristive crossbar arrays, however, suffer from an inherent sneak-path problem due to partially selected devices [21]. Although it is possible to avoid the effect of the sneakpath problem during read operations on memristive-based crossbars [9], [21], the energy consumption and current requirements in the worst-case scenario while reading and writing impose design constrains that end up being the limiting factors for scaling.The complementary resistive switch or CRS was proposed as a way to mitigate the sneak-path problem [8]. A CRS is formed by two anti-serially connected memristors and stores binary information as an internal configuration rather than as an actual resistance value, as done in a memristor. Both configurations in a CRS have a high resistance, which greatly reduces the data dependencies and parasitic current paths due to partially selected devices.In contrast to the non-destructive read operation of a single memristor [13], the read operation in a CRS is destructive by nature and must be followed by a restore, i.e., write operation [8]. This type of write amplification negatively affects the endurance of CRS-based memories and results in excessive energy...

Toward large-scale access-transistor-free memristive crossbars

“…In [25], the destructive read problem of CRS cells is addressed. The authors proposed HReRAM, a hybrid crossbar structure formed by CRS cells that can act both as a memristor and as a CRS, a behavior that has been observed in TaO xbased single memory cells [26].…”

Architecting energy efficient crossbar-based memristive random-access memories

“…2(a). Such behavior can be obtained by highly nonlinear memristors [3], and can be also achieved using complementary resistive switches [25], [26]. Applying voltages below a threshold voltage Vth neither generates a significant current nor changes the device resistance.…”