HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA

Madhok, Shivani; Pandey, Bishwajeet; Kaur, Amanpreet; Minver, Mohamed Hashim; Hussain, Dil Muhammad Akbar

doi:10.14257/ijca.2015.8.8.05

Cited by 19 publications

(8 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…multiplier based on HSTL IO Standard [6], DES Algorithm Design [7] and Arithmetic Logic Unit Design on 28nm FPGA using SSTL [8] .…”

Section: A Cmos-based Tactile Sensor For Continuous Blood Pressure Momentioning

confidence: 99%

Wrist Band Design using Low Power Virtex6 FPGA for Monitoring Blood Pressure

Sharma¹

2017

GJECS

View full text Add to dashboard Cite

Abstract-Out of control blood pressure whether it is low or high can be dangerous and major cause of heart disease. The people suffering from blood pressure problems are increasing day by day. The main objective of this paper is to make a wrist band which can monitor the blood pressure of our body at any time. The approach is to make it consume low power for its operation. Technique applied for doing same is capacitance scaling using Field Programmable gate Array using Xilinx software. The power consumption at frequency 0.2GHz, 1GHz, 2GHz, 20GHz and 200GHz is calculated for Low PowerVirtex6 FPGA.

show abstract

“…multiplier based on HSTL IO Standard [6], DES Algorithm Design [7] and Arithmetic Logic Unit Design on 28nm FPGA using SSTL [8] .…”

Section: A Cmos-based Tactile Sensor For Continuous Blood Pressure Momentioning

confidence: 99%

Wrist Band Design using Low Power Virtex6 FPGA for Monitoring Blood Pressure

Sharma¹

2017

GJECS

View full text Add to dashboard Cite

show abstract

“…We are using thermal scaling and frequency scaling in place of Mobile DDR IO standards. In this reference [2] researcher have designed an energy efficient Multiplier using Nikhilam Navatashcaramam Dashatah Vedic technique. Another researcher have performed power dissipation analysis of DES algorithm, implemented on a 28nm FPGA [3].…”

Section: Related Workmentioning

confidence: 99%

Design of Energy Efficient Sinusoidal PWM Waveform Generator on FPGA

Pandey

Tomar

Dhirani

et al. 2017

IJSIP

Self Cite

View full text Add to dashboard Cite

show abstract

“…There are more paper like design of multiplier based on HSTL IO Standard [5], DES Algorithm Design which is low power [6] and Arithmetic Logic Unit Design on 28nm FPGA which is based on SSTL [7] which works in the same area to reduce the amount of power used and hence making the performance curve increase by different types of scaling.…”

Section: Regular Expression Matching For Reconfigurable Packet Inspecmentioning

confidence: 99%

Reduction in power consumption of packet counter on VIRTEX-6 FPGA by frequency scaling

Pandey¹,

Pandey²,

Hussain

2017

2017 Saudi Arabia Smart Grid (SASG)

Self Cite

View full text Add to dashboard Cite

In Today's World it is very easy to share the information fast may be within seconds or even may be less. However, the required data is shared so it is the main concern. We share data over web and data is transferred in the form of packets. How these data packets are transmitted is all concept of Networking. This paper focuses on making of a packet counter that consumes least power for its operation. Packet counters are used for counting data packets at transmitter and receiver end and hence finding the number of packets or data lost in whole process. The Design is implemented for LVCOMS_25, LVDCI_25, SSTL_15 and HSTL_III I/O standards for Virtex6 Field Programmable Gate Array. Percentage Change in power consumed is calculated by scaling frequency and hence efficient packet counter is achieved.

show abstract

HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA

Abstract: Abstract

Cited by 19 publications

References 19 publications

Wrist Band Design using Low Power Virtex6 FPGA for Monitoring Blood Pressure

Wrist Band Design using Low Power Virtex6 FPGA for Monitoring Blood Pressure

Design of Energy Efficient Sinusoidal PWM Waveform Generator on FPGA

Reduction in power consumption of packet counter on VIRTEX-6 FPGA by frequency scaling

Contact Info

Product

Resources

About