Hybrid cache architecture replacing SRAM cache with future memory technology

Lee, Suji; Jung, Jongpil; Kyung, Chong-Min

doi:10.1109/iscas.2012.6271803

Cited by 11 publications

(4 citation statements)

References 9 publications

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“…As the capacity of cache becomes larger, more sophisticated hybrid memory system architecture and operation mechanism can deliver superior performance and energy efficiency than the conventional cache memory system with only SRAM and/or MRAM. Limited studies [1], [2], [3] have been conducted to design efficient hybrid cache memory systems with non-volatile memory. Wu et al [1] evaluated several possibilities to accommodate on-chip cache hierarchies based on Hybrid Cache Architecture (HCA).…”

Section: Hybrid Cache Memory Based On Sram-mrammentioning

confidence: 99%

“…The LHCA (inter cache level) used desperate memory technology to make levels in a cache hierarchy and provided 7% geometric mean IPC (intruction per cycle) improvement over baseline cache while as RHCA (intra cache level) partitioned a single level cache into multiple regions and provided an improvement of 12% IPC over baseline cache under same area constraints. To alleviate the performance degradation caused by long access latency of MRAM with small SRAM cache, a way partitioned hybrid cache memory system constructed with SRAM and MRAM was proposed by Lee et al [2]. The SRAM tecnology was used to built level 1 cache where as level 2 caches were manufactured using S, D and MRAM technologies.…”

Section: Hybrid Cache Memory Based On Sram-mrammentioning

confidence: 99%

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A study of recent advances in cache memories

Banday

Khan

2014

2014 International Conference on Contemporary Computing and Informatics (IC3I)

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Registers within a processor, cache within, on, or outside the processor, and virtual memory on the disk drive builds memory hierarchy in modern computer systems. The principle of locality of reference makes this memory hierarchy work efficiently. In recent years, cache organizations and designs have witnessed several advances that have not only improved their performance such as hit rates, speed, latency, energy consumption, etc. but various new designs and organizations for chip multi-processors such as multilevel caches, Non-Uniform Cache Access (NUCA), hybrid caches, etc. have also emerged. This paper presents a study of current competing processors in terms of various factors determining performance and throughput of cache organization and design. To evaluate their performance and viability, it reviews recent cache trends that include hybrid cache memory, non-uniform cache architecture, energy efficient replacement algorithms, cache memory programming, software defined caches and emerging techniques for making cache reliable against soft errors. It discusses the pros and cons of emerging cache architectures and designs.

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Section: Hybrid Cache Memory Based On Sram-mrammentioning

confidence: 99%

Section: Hybrid Cache Memory Based On Sram-mrammentioning

confidence: 99%

A study of recent advances in cache memories

Banday

Khan

2014

2014 International Conference on Contemporary Computing and Informatics (IC3I)

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“…This can be achieved by the advances in storage and memory technologies. The scalability of fast on-chip cache implemented by SRAM is significantly restricted by high leakage power and the reliability issues caused due to process variations [1,2]. Therefore, efforts have been made to identify technological alternatives to SRAM for achieving non-volatility, high performance, ultrafast speed, and low power consumption.…”

Section: Introductionmentioning

confidence: 99%

Multi-bit MRAM based high performance neuromorphic accelerator for image classification

Verma,

Soni,

Nisar

et al. 2024

Neuromorph. Comput. Eng.

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Binary neural networks (BNNs) are the most efficient solution to bridge the design gap of the hardware implementation of neural networks in a resource-constrained environment. Spintronics is a prominent technology among emerging fields for next-generation on-chip non-volatile memory (NVM). Spin transfer torque (STT) and spin-orbit torque (SOT) based magnetic random-access memory (MRAM) offer non-volatility and negligible static power. Over the last few years, STT and SOT-based multilevel spintronic memories have emerged as a promising solution to attain high storage density. This paper presents the operation principle and performance evaluation of spintronics-based single-bit STT and SOT MRAM, dual-level cells (DLCs), three-level cells (TLCs), and four-level cells (FLCs). Further, multi-layer perceptron (MLP) architectures have been utilized to perform MNIST image classification with these multilevel devices. The performance of the complete system level consisting of crossbar arrays with various MRAM bit cells in terms of area, energy, and latency is evaluated. The throughput efficiency of the BNN accelerator using TLCs is 26.6X, and 3.61X higher than conventional single-bit STT-MRAM, and SOT-MRAM respectively.

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“…However, NVM also suffers from challenges, such as limited write endurance and large write power consumption [5,6]. In order to solve these problems, hybrid cache architecture of SRAM and NVM is generally adopted in 3D CMPs [7][8][9][10][11]. Wu et al [8] proposed a read-write-aware hybrid cache architecture, in which the cache is divided into read and write portions.…”

Section: Introductionmentioning

confidence: 99%

A Cache Fill and Migration Policy for STT-RAM-Based Multi-Level Hybrid Cache in 3D CMPs

Wang

et al. 2019

Electronics

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Recently, in 3D Chip-Multiprocessors (CMPs), a hybrid cache architecture of SRAM and Non-Volatile Memory (NVM) is generally used to exploit high density and low leakage power of NVM and a low write overhead of SRAM. The conventional access policy does not consider the hybrid cache and cannot make good use of the characteristics of both NVM and SRAM technology. This paper proposes a Cache Fill and Migration policy (CFM) for multi-level hybrid cache. In CFM, data access was optimized in three aspects: Cache fill, cache eviction, and dirty data migration. The CFM reduces unnecessary cache fill, write operations to NVM, and optimizes the victim cache line selection in cache eviction. The results of experiments show that the CFM can improve performance by 24.1% and reduce power consumption by 18% when compared to conventional writeback access policy. This paper proposes a cache fill and migration policy (CFM) for multi-level hybrid cache in 3D CMPs. The CFM optimizes data access in three aspects: Cache fill, cache eviction and data migration compared to the conventional writeback access policy. Firstly, the CFM can effectively reduce the unnecessary cache fill and the write operations to the NVM if a cache fill is required. Secondly, the CFM optimizes the victim cache line selection in cache eviction to reduce the data migration overhead of the dirty victim. Finally, the CFM analyzes the migration cost in multi-level hybrid cache architecture and proposes two migration principles to minimize the migration cost. These two migration principles are suitable in dark silicon era, in which case some open cache banks become closed and some closed cache banks become open (we call this cache architecture dynamically reconfiguration). The results show that in multi-level hybrid cache architecture, the CFM can achieve performance improvement and power saving effectively.The rest of the paper is organized as follows. Section 2 analyzes the problems in conventional writeback access policy in hybrid cache. Section 3 presents the proposed cache fill and migration policy. Section 4 shows the experimental results and finally the conclusion is given in Section 5.

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Hybrid cache architecture replacing SRAM cache with future memory technology

Cited by 11 publications

References 9 publications

A study of recent advances in cache memories

A study of recent advances in cache memories

Multi-bit MRAM based high performance neuromorphic accelerator for image classification

A Cache Fill and Migration Policy for STT-RAM-Based Multi-Level Hybrid Cache in 3D CMPs

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