Abstract-Address base-plus-offset summing is merged into the decode structure of this 64-KByte (512-Kbit), four-way setassociative cache. This address adder avoids time-consuming carry propagation by using an A + B = K A + B = K A + B = K equality test. The combined add and access operations are implemented using delayed-reset logic and a 0.25-m process. This wave pipelined RAM achieves a 1.6-ns cycle time and 2.6-ns latency for the combined address add and cache access.

Transparent conductive film on a plastic substrate is a critical component in low cost, flexible and lightweight optoelectronics. CVD graphene transferred from copper- to ethylene vinyl acetate (EVA)/polyethylene terephthalate (PET) foil by hot press lamination has been reported as a robust and affordable alternative to manufacture highly flexible and conductive films. Here, we demonstrate that annealing the samples at 60 ∘C under a flow of nitrogen, after wet etching of copper foil by nitric acid, significantly enhances the Hall mobility of such graphene films. Raman, Scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS) were used to evaluate the morphology and chemical composition of the graphene.

The authors wish to make following corrections in this paper [...]

Registers within a processor, cache within, on, or outside the processor, and virtual memory on the disk drive builds memory hierarchy in modern computer systems. The principle of locality of reference makes this memory hierarchy work efficiently. In recent years, cache organizations and designs have witnessed several advances that have not only improved their performance such as hit rates, speed, latency, energy consumption, etc. but various new designs and organizations for chip multi-processors such as multilevel caches, Non-Uniform Cache Access (NUCA), hybrid caches, etc. have also emerged. This paper presents a study of current competing processors in terms of various factors determining performance and throughput of cache organization and design. To evaluate their performance and viability, it reviews recent cache trends that include hybrid cache memory, non-uniform cache architecture, energy efficient replacement algorithms, cache memory programming, software defined caches and emerging techniques for making cache reliable against soft errors. It discusses the pros and cons of emerging cache architectures and designs.