Hybrid-cell register files design for improving NBTI reliability

Gong, Na; Jiang, Shanshan; Wang, Jinhui; Aravamudhan, B.; Sekar, K.; Sridhar, R.

doi:10.1016/j.microrel.2012.06.045

Cited by 11 publications

(8 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The subsequent level of comparators determines if all ∆ e j and all ∆ b k from the current subwavefront are equal to ∆ e and ∆ b , respectively, from the first subwavefront. For this purpose, ∆ e and ∆ b are stored in two intermediate buffers controlled by the W en ∆ signal, which is only activated in the deltas C 0 -C 15 from the previous subwavefront, this component is stored in the buffer controlled by W en c . This signal is only activated in those states referring to a possibly compressible register (i.e., deltas C 0 -C 15 , deltas C 16 -C 31 , and deltas C 32 -C 47 ).…”

Section: Compression Unitmentioning

confidence: 99%

An Aging-Aware GPU Register File Design Based on Data Redundancy

Valero

Candel

Gracia

et al. 2019

IEEE Trans. Comput.

View full text Add to dashboard Cite

Nowadays, GPUs sit at the forefront of high-performance computing thanks to their massive computational capabilities. Internally, thousands of functional units, architected to be fed by large register files, fuel such a performance. At deep nanometer technologies, the SRAM memory cells that implement GPU register files are very sensitive to the Negative Bias Temperature Instability (NBTI) effect. NBTI ages cell transistors by degrading their threshold voltage V th over the lifetime of the GPU. This degradation, which manifests when a cell keeps the same logic value for a relatively long period of time, compromises the cell read stability and increases the transistor switching delay, which can lead to wrong read values and eventually exceed the processor cycle time, respectively, so resulting in faulty operation. This work proposes architectural mechanisms leveraging the redundancy of the data stored in GPU register files to attack NBTI aging. The proposed mechanisms are based on data compression, power gating, and register address rotation techniques. All these mechanisms working together balance the distribution of logic values stored in the cells along the execution time, reducing both the overall V th degradation and the increase in the transistor switching delays. Experimental results show that a conventional GPU register file suffers the worst case for NBTI, since a significant fraction of the cells maintain the same logic value during the entire application execution (i.e., a 100% '0' and '1' duty cycle distributions). On average, the proposal reduces these distributions by 58% and 68%, respectively, which translates into V th degradation savings by 54% and 62%, respectively.

show abstract

Section: Compression Unitmentioning

confidence: 99%

An Aging-Aware GPU Register File Design Based on Data Redundancy

Valero

Candel

Gracia

et al. 2019

IEEE Trans. Comput.

View full text Add to dashboard Cite

show abstract

“…Given that the tag array is much smaller than the data array, resilient technologies could be used to address tag wearout. For example, resilient 8T cells introduce a 19% area overhead compared to typical 6T cells [13]. According to CACTI [14], implementing the tags with 8T cells results in just a 1.95% area overhead for a 16KB L1 cache.…”

Section: Proposed Architectural Techniquesmentioning

confidence: 99%

“…For example, Wang et al [26] divide the integer register file into two halves and balance the duty cycle distribution in the upper half where most entries hold '0'. Gong et al [13] include robust 8T cells in the register file design, which store the most NBTI-vulnerable bits, while the remaining data bits are stored in typical 6T cells. Kothawade et al [27] equalize the NBTI stress across the register file by altering the register decoding scheme.…”

Section: Related Workmentioning

confidence: 99%

On Microarchitectural Mechanisms for Cache Wearout Reduction

Valero

Miralaei

Petit

et al. 2017

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI) are two of the main deleterious effects that increase a transistor's threshold voltage over the lifetime of a microprocessor. This voltage degradation causes slower transistor switching and eventually can result in faulty operation. HCI manifests itself when transistors switch from logic '0' to '1' and vice versa, whereas BTI is the result of a transistor maintaining the same logic value for an extended period of time. These failure mechanisms are especially acute in those transistors used to implement the SRAM cells of first-level (L1) caches, which are frequently accessed, so they are critical for performance, and they are continuously aging. This paper focuses on microarchitectural solutions to reduce transistor aging effects induced by both HCI and BTI in the data array of L1 data caches. First, we show that the majority of cell flips are concentrated in a small number of specific bits within each data word. In addition, we also build upon previous studies showing that logic '0' is the most frequently written value in a cache by identifying which cells hold a given logic value for a significant amount of time. Based on these observations, this work introduces a number of architectural techniques that spread the number of flips evenly across memory cells and reduce the amount of time that logic '0' values are stored in the cells by switching off specific data bytes. Experimental results show that the threshold voltage degradation savings range from 21.8% to 44.3% depending on the application.

show abstract

“…Most recently, Siddiqua and Gurumurthi [21] proposed recovery boosting RF which allows both pMOS devices in the bit-cell to be put into the recovery mode. In [22], a hybrid-cell RF design was presented to mitigate NBTI-induced degradation by storing more vulnerable data bits in the robust 8T cells and the less vulnerable bits in the conventional 6T cells.…”

Section: B Related Work On Reliable Rf Designmentioning

confidence: 99%

“…Nevertheless, none of these techniques have accounted for the lifetime reliability issue to make RF tolerant to aging effect. On the other hand, previous NBTI/PBTI mitigation techniques [19]- [22] lead to considerable power consumption overhead, which significantly influence the power efficiency of RF.…”

Section: Introductionmentioning

confidence: 99%

TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors

Gong

Wang

Jiang

et al. 2015

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Modern microprocessors employ register files (RFs) for performance enhancement and achieving instruction level parallelism simultaneously. However, RF incurs large power consumption owing to the highly frequent access. Meanwhile, as technology scales, bias temperature instability has become a major reliability concern for RF designers. This paper presents an aging-aware trimodal register file (TM-RF) design to enhance the power efficiency. As instructions pass through the pipeline, TM-RF places the bit-cells in different modes based on the register activity, thereby achieving significant power reduction. To meet design constraints of different applications, we present four schemes to implement the proposed design, providing design flexibility. Additionally, with device selection and worst case sizing methodology, we mitigate aging-effect-induced RF reliability degradation. Simulation results on SPEC 2000 benchmarks demonstrate that TM-RF achieves up to 81.4% power savings and 17% reliability improvement on average, with minimal impact on performance.Index Terms-Leakage current, low power, bias temperature instability (NBTI/PBTI), process variation, register file (RF). 1063-8210

show abstract

Hybrid-cell register files design for improving NBTI reliability

Cited by 11 publications

References 21 publications

An Aging-Aware GPU Register File Design Based on Data Redundancy

An Aging-Aware GPU Register File Design Based on Data Redundancy

On Microarchitectural Mechanisms for Cache Wearout Reduction

TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors

Contact Info

Product

Resources

About