Hybrid clock synchronization: Conditions for existence of a steady state in a mesh network

Yahata, Haruki

doi:10.1002/(sici)1520-6424(199811)81:11<77::aid-ecja8>3.0.co;2-m

Cited by 1 publication

(2 citation statements)

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“…Thus, the items to be considered in synchronization gain setting for the pull-in are clear in the hybrid clock synchronization network configuration reported by the author [2]. There still remain topics for study such as the transient response of the synchronization network and analysis of the phase jitter for the noise.…”

Section: Discussionmentioning

confidence: 99%

“…Further, the sufficient condition has been obtained when the local network is a mesh net. From this condition, it is found that the mesh-type clock synchronization network degrades the reliability of synchronization on accidental failure and that a method based on the ring type is better as a synchronization network configuration reliable for a one-point failure [2]. The derivation of the range for which a stable phase condition exists in the network is equivalent to that of the synchronization sustaining range of the network.…”

Section: Introductionmentioning

confidence: 99%

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Hybrid clock synchronization: the pull-in range of a ring network

Yahata

1999

Electron. Comm. Jpn. Pt. I

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The hybrid clock synchronization method locks subordinately to the external wide‐area network while mutual locking is used within the network. This method has excellent reliability as a clock synchronization method for a local network. By using a dual‐input phase lock loop (PLL), nodes that can obtain clocks externally are connected in a ring and are used as the higher level nodes in the proposed method. In this configuration of the synchronization network, other nodes are treated as lower‐level nodes which obtain clocks from higher‐level nodes. In this paper, the pull‐in range of the synchronization network in this configuration is obtained. First, the waveform connection condition within the PLL is obtained when the output frequency of the PLL coincides with that of one of the inputs (with a smaller synchronization gain). From this result, the range is derived for the output frequency to move toward the input frequency. This is considered as the operating pull‐in range. It is shown that the pull‐in range of the entire ring network is the minimum value of the dynamic pull‐in range among all of the nodes. Also, the pull‐in range of the lower level nodes is considered in the state after convergence of the ring network. It is shown that the pull‐in range becomes the minimum in the situation where the phases of the two inputs are opposite. The above observations are confirmed by simulation. © 1999 Scripta Technica, Electron Comm Jpn Pt 1, 82(6): 45–59, 1999

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%