Hybrid CMOS/Memristor Circuit Design Methodology

Maheshwari, Sachin; Stathopoulos, Spyros; Wang, Jiaqi; Serb, Alexantrou; Pan, Yihan; Mifsud, Andrea; Leene, Lieuwe B.; Shen, Jiawei; Papavassiliou, Christos; Constandinou, Timothy G.; Prodromakis, Themistoklis

doi:10.48550/arxiv.2012.02267

Cited by 4 publications

(5 citation statements)

References 53 publications

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“…As mentioned, the memristor's Verilog-A model is obtained from the measurement [38]. The 0.18 um CMOS spike models are obtained from the Generic 018 CMOS PDK of CA-DENCE [34]. One more thing to note is that the DAC and VCO used in Figure 7 are also modeled using Verilog-A for saving the simulation time and the models are from the chip measurement [36,37].…”

Section: Resultsmentioning

confidence: 99%

“…A digital part of the neural network's controller in Figure 4d is shown in Figure 6. Basically, the circuits shown in Figure 6 are designed by a Generic PDK of 0.18 um CMOS technology provided from CADENCE CAD software (Virtuoso version 6.1.8-64b, and Spectre version 20.1.0.068) [34]. The circuits shown in Figure 6 are scalable basically because they are designed by common CMOS design techniques.…”

Section: Methodsmentioning

confidence: 99%

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Memristor–CMOS Hybrid Circuits Implementing Event-Driven Neural Networks for Dynamic Vision Sensor Camera

Yoon,

Oh,

Cho

et al. 2024

Micromachines

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For processing streaming events from a Dynamic Vision Sensor camera, two types of neural networks can be considered. One are spiking neural networks, where simple spike-based computation is suitable for low-power consumption, but the discontinuity in spikes can make the training complicated in terms of hardware. The other one are digital Complementary Metal Oxide Semiconductor (CMOS)-based neural networks that can be trained directly using the normal backpropagation algorithm. However, the hardware and energy overhead can be significantly large, because all streaming events must be accumulated and converted into histogram data, which requires a large amount of memory such as SRAM. In this paper, to combine the spike-based operation with the normal backpropagation algorithm, memristor–CMOS hybrid circuits are proposed for implementing event-driven neural networks in hardware. The proposed hybrid circuits are composed of input neurons, synaptic crossbars, hidden/output neurons, and a neural network’s controller. Firstly, the input neurons perform preprocessing for the DVS camera’s events. The events are converted to histogram data using very simple memristor-based latches in the input neurons. After preprocessing the events, the converted histogram data are delivered to an ANN implemented using synaptic memristor crossbars. The memristor crossbars can perform low-power Multiply–Accumulate (MAC) calculations according to the memristor’s current–voltage relationship. The hidden and output neurons can convert the crossbar’s column currents to the output voltages according to the Rectified Linear Unit (ReLU) activation function. The neural network’s controller adjusts the MAC calculation frequency according to the workload of the event computation. Moreover, the controller can disable the MAC calculation clock automatically to minimize unnecessary power consumption. The proposed hybrid circuits have been verified by circuit simulation for several event-based datasets such as POKER-DVS and MNIST-DVS. The circuit simulation results indicate that the neural network’s performance proposed in this paper is degraded by as low as 0.5% while saving as much as 79% in power consumption for POKER-DVS. The recognition rate of the proposed scheme is lower by 0.75% compared to the conventional one, for the MNIST-DVS dataset. In spite of this little loss, the power consumption can be reduced by as much as 75% for the proposed scheme.

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Section: Resultsmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

Memristor–CMOS Hybrid Circuits Implementing Event-Driven Neural Networks for Dynamic Vision Sensor Camera

Yoon,

Oh,

Cho

et al. 2024

Micromachines

View full text Add to dashboard Cite

show abstract

“…In order to eliminate this offset, scholars have carried out relevant research and achieved remarkable results [18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34]. They can be divided into two categories: one is completely composed of memristors.…”

Section: Introductionmentioning

confidence: 99%

Memristor-Based Read/Write Circuit with Stable Continuous Read Operation

Bao

Zheng

et al. 2022

Electronics

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In recent years, computation-intensive applications, such as artificial intelligence, video processing and encryption, have been developing rapidly. On the other hand, the problems of “storage wall” and “power consumption wall” for the traditional storage and computing separated architectures limit the computing performance. The computational circuits and memory cells based on nonvolatile memristors are unified and become a competitive solution to this problem. However, there are various problems that prevent memristor-based circuits from entering practical applications, one of which is the memristor state deviation problem caused by continuous reading. In this paper, we study some circuits studied by predecessors on read/write circuit, compare the experimental results, analyze the reason for the resistance state deviation of memristor, and put forward a new parallel structure of memristor based on opposite polarity. The logic “1” and logic “0” are represented by the positive and negative voltage difference of two memristors with opposite polarity, which can effectively alleviate the problem of the resistance state deviation caused by continuous reading. A reading voltage of 2 V is applied to the four circuits at the same time, and continuous reading is carried out until the output voltage becomes stable. The voltage offset of the optimized circuit when reading logic “0” is reduced to 78 mV, which is significantly smaller than that of other circuits. In addition, when reading logic “1”, it has the effect of enhancing the information stored in the memristor.

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“…Despite of their success, conventional type of memories have major disadvantages. Volatile memories suffer of high power consumption and loss of data on power off, while non volatile memories require high write voltage and suffer of low endurance and low speed [4], [11].…”

Section: Introductionmentioning

confidence: 99%

“…A promising type of memory which satisfies these criteria is the Resistive Random Access Memory (RRAM). RRAM uses memristors in its memory cells [3], [11], [14], [15].…”

Section: Introductionmentioning

confidence: 99%

An Open-Source RRAM Compiler

Antoniadis¹,

Mifsud²,

Feng³

et al. 2021

Preprint

Self Cite

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Memory compilers are necessary tools to boost the design procedure of digital circuits. However, only a few are available to academia. Not only this, but conventional memories suffer of volatility, high power consumption, high write voltage and low endurance. Resistive Random Access Memory (RRAM) seems to be a potential candidate of future digital memories, as it is characterised by high density, high speed and non volatility. To the best of the authors' knowledge, this paper presents the first open source RRAM Compiler for automatic memory generation, verification and timing characterisation. The RRAM compiler is written with Cadence SKILL programming language and is integrated in Cadence Virtuoso and Innovus environment. The verification procedure takes place in Siemens Mentor Calibre tool. A novel RRAM architecture is presented and its peripheral circuits are explained. Additionally, this paper analyses the results of a plethora of M x N RRAMs generated by the compiler, up to M = 128, N = 64 and word size B = 16 bits, for clock frequency equal to 12.5 MHz. Finally, the compiler achieves density of up to 0.024 Mb/mm 2 for a 180 nm technology.

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Hybrid CMOS/Memristor Circuit Design Methodology

Cited by 4 publications

References 53 publications

Memristor–CMOS Hybrid Circuits Implementing Event-Driven Neural Networks for Dynamic Vision Sensor Camera

Memristor–CMOS Hybrid Circuits Implementing Event-Driven Neural Networks for Dynamic Vision Sensor Camera

Memristor-Based Read/Write Circuit with Stable Continuous Read Operation

An Open-Source RRAM Compiler

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