Hybrid cross correlation and line-scan alignment strategy for CMOS chips electron-beam lithography processing

Abstract

In this paper, we show an alignment strategy based on a hybrid strategy using cross correlation and line-scan alignment to address the challenge for CMOS integrated circuit postprocessing using electron-beam lithography. Due to design rules imposed by the foundries at the 130 nm node and below, classical line-scan alignment is not possible, and marker shapes are limited. The shape of the marker is essential for cross-correlation alignment. By measuring accurately the alignment offset between two lithography steps with different marker shapes compatible with the design rules, we tested the influence of the marker shape in the performance of the cross-correlation alignment. We present a method based on a white noise generated array to design high-performance markers for cross correlation, compatible with CMOS technology, by increasing the sharpness of their autocorrelation peak. We show that the alignment performances can even be improved using a hybrid strategy with cross-correlation and line-scan alignment and reaches a mean offset of 5.2 nm on a CMOS substrate.