Hybrid data mining approach for pattern extraction from wafer bin map to improve yield in semiconductor manufacturing

Wafer level characterisation of microelectrodes for electrochemical sensing applications

“…Wafer-level mapping of devices can be a powerful tool for understanding fabrication processes, as well as quantifying parameters such as yield and uniformity [16]. To demonstrate that capability can be expanded to electrochemical sensors, the same cyclic voltammetry measurements were performed across nine neighbouring electrodes shown in Fig.…”

Correlation Analysis on Semiconductor Process Variables Using CCA(Canonical Correlation Analysis) : Focusing on the Relationship between the Voltage Variables and Fail Bit Counts through the Wafer Process

“…공정 간의 상관관계를 이용한 기존 연구로서 공 정 조건 간의 상관관계를 파악하여 최적 공정 조건을 찾는 연 구가 진행되었고 (Byun et al, 1998) 와 PCM(Process Control Monitoring) 데이터를 활용 (Ludwig, 2000)하였다. 패키 지 테스트의 결과를 예측하기 위해서 웨이퍼 검사 데이터 (An et al, 2009)를 활용하거나 웨이퍼 빈 맵(Wafer Bin Map)을 활용 (Hsu et al, 2007) 하는 등 다양한 연구가 진행되었다. 패키지 테스트 결과를 예측하는 연구에서는 칩에 대한 결함 유형을 설명하기 위한 코드로 빈(BIN) 정보 (Quirk et al, 2001), PCM 테 스트 정보, 불량결점 수(Fail Bit Count), 웨이퍼의 칩 좌표 정보 등을 주로 이용하였다.…”

An Analytic Framework of Design for Semiconductor Manufacturing

“…Semiconductor fabrication facilities (fabs) can only maintain competitive advantages by effectively controlling process variation, fast yield ramp up, and quick response to yield excursion, especially when the complexity of the process and product increase rapidly. In particular, most of applications using various data mining technologies included root cause identification [8,9], process improvement [10], defect pattern diagnosis [11], equipment backup control [12], cycle time prediction [13,14], demand forecast [15,16], and virtual metrology [17,18]. Most applications are yield improvement for wafer manufacturing and test phase.…”