Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors

Azambuja, Jose Rodrigo; Kastensmidt, Fernanda Lima; Becker, J.

doi:10.1007/978-3-319-06340-9

Cited by 13 publications

(7 citation statements)

References 11 publications

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“…To do that, fault-tolerance techniques employ redundancy in terms of 1) hardware, 2) software, 3) information, and 4) time beyond what is needed for the normal operation of the system. In the following, we explain the different fault-tolerance techniques that belong to the four mentioned redundancy types as introduced in [16], [17], [24].…”

Section: Fault-tolerance Techniquesmentioning

confidence: 99%

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A Survey of Fault-Tolerance Techniques for Embedded Systems From the Perspective of Power, Energy, and Thermal Issues

et al. 2022

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The relentless technology scaling has provided a significant increase in processor performance, but on the other hand, it has led to adverse impacts on system reliability. In particular, technology scaling increases the processor susceptibility to radiation-induced transient faults. Moreover, technology scaling with the discontinuation of Dennard scaling increases the power densities, thereby temperatures, on the chip. High temperature, in turn, accelerates transistor aging mechanisms, which may ultimately lead to permanent faults on the chip. To assure a reliable system operation, despite these potential reliability concerns, fault-tolerance techniques have emerged. Specifically, fault-tolerance techniques employ some kind of redundancies to satisfy specific reliability requirements. However, the integration of fault-tolerance techniques into real-time embedded systems complicates preserving timing constraints. As a remedy, many task mapping/scheduling policies have been proposed to consider the integration of fault-tolerance techniques and enforce both timing and reliability guarantees for real-time embedded systems. More advanced techniques aim additionally at minimizing power and energy while at the same time satisfying timing and reliability constraints. Recently, some scheduling techniques have started to tackle a new challenge, which is the temperature increase induced by employing fault-tolerance techniques. These emerging techniques aim at satisfying temperature constraints besides timing and reliability constraints. This paper provides an in-depth survey of the emerging research efforts that exploit fault-tolerance techniques while considering timing, power/energy, and temperature from the real-time embedded systems' design perspective. In particular, the task mapping/scheduling policies for fault-tolerance real-time embedded systems are reviewed and classified according to their considered goals and constraints. Moreover, the employed fault-tolerance techniques, application models, and hardware models are considered as additional dimensions of the presented classification. Lastly, this survey gives deep insights into the main achievements and shortcomings of the existing approaches and highlights the most promising ones.INDEX TERMS Fault-tolerance, embedded systems, real-time computing, scheduling, power/energy minimization, thermal-aware design.

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Section: Fault-tolerance Techniquesmentioning

confidence: 99%

“…Fault-tolerance techniques can be classified into three broad categories based on exploited redundancy types including: i) hardware-based, ii) software-based, and iii) hybrid techniques [24].…”

Section: ) Software Redundancymentioning

confidence: 99%

A Survey of Fault-Tolerance Techniques for Embedded Systems From the Perspective of Power, Energy, and Thermal Issues

et al. 2022

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“…All such processor-sensitive faults are categorized as Transient Faults (TFs) and Intermittent Faults (IFs). Some of the typical processor’s sensitivity faults are illustrated in Figure 4 (Azambuja et al , 2014). Figure 4(a) explains the periodic occurrence of both TFs and IFs.…”

Section: Possible Processor Sensitivity Failure Modes In Industrial M...mentioning

confidence: 99%

Simulation and empirical validation of new sensitivity based reliability analysis technique for processors deployed in industrial drives

Chitra

2022

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Purpose The purpose of this study is to extend a sensitivity-based reliability technique for the processors deployed in industrial drive (ID). Design/methodology/approach The processor provides flexible operation, re-configurability, and adaptable compatibility in industrial motor drive system. A sensitivity-based model allows a robust tool for validating the system design. Sensitivity is the probability of a partial failure rate for a distributed variable; sensitivity and failure rates are also complementary. Conversely, traditional power electronic components reliability estimating standards have overlooked it, and it is essential to update them to account for the sensitivity parameter. A new sensitivity-based reliability prediction methodology for a typical 32-bit microprocessor operating at 30ºC deployed in ID is presented to fill this gap. The proposed techniques are compared with the estimated processor reliability values obtained from various reliability standards using the validated advanced logistics development tool. The main contribution of this work is to provide a sensitivity extended reliability method over the conventional method directing toward improving reliability, availability, and maintainability in the design of ID. Findings The analysis shows that the sensitivity of the processor’s circuit increases due to increases in complexity of the system by reducing the overall mean time between failure upon comparing among conventional reliability standards. Originality/value The significance of this paper lies in the overall, sensitivity-based reliability technique for processors in comparison to the traditional reliability complexity in IDs.

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“…The data corruption in these low-level memory units is fraught with data corruption at the end of the executable program and the functional interruptions of a system, whose repair is often solved only by a hardware reset. In addition, the corrupted data in the low-level memory can spread to the high-level memory [13].…”

Section: Introductionmentioning

confidence: 99%

Upset-resilient RAM on STG DICE memory elements with the spaced transistors into two groups

2016

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Abstract⎯The first experimental test of new DICE memory cells with the transistors spaced into two groups (Spaced Transistor Groups DICE-STG DICE), composed on a 65-nm CMOS static RAM proved their high upset resilience. The STG DICE memory cells have two communication wires between the two groups of transistors that made it possible to use the striping of groups of transistors to increase the distances between sensitive nodes of cells up to 2.32-3.09 μm at a small increase in cell area. The blocks of 65-nm 128 × 32-bit CMOS RAM cache and 32 × 64-bit multiport RAM based on the STG DICE cells are characterized by upset thresholds lying in the range of 3.55-4.05 nJ of the laser pulse energy with a pulse duration of 70 ps and diameter of the spot of 3.5 μm. These threshold values exceed the upset thresholds of 65-nm CMOS RAM on 6T memory cells by factors of 20 for RAM cache and 3.5 for multiport RAM. In STG DICE RAM multiple upsets are absent in contrast to RAM based on 6T-cells.

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Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors

Cited by 13 publications

References 11 publications

A Survey of Fault-Tolerance Techniques for Embedded Systems From the Perspective of Power, Energy, and Thermal Issues

A Survey of Fault-Tolerance Techniques for Embedded Systems From the Perspective of Power, Energy, and Thermal Issues

Simulation and empirical validation of new sensitivity based reliability analysis technique for processors deployed in industrial drives

Upset-resilient RAM on STG DICE memory elements with the spaced transistors into two groups

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