Hybrid Memory Buffer Microarchitecture for High-Radix Routers

Li, Cunlu; Dong, Dezun; Liao, Xiangke; Kim, John

doi:10.1109/tc.2021.3076431

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2023

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“…IEICE Electronics Express, Vol.xx, No.xx, xx-xx to 2 cycles at 1 GHz clock frequency. Considering most hierarchical routers work under 1 GHz clock frequency[18], a 2-cycle write latency STT-RAM is adopted in our design accordingly. The parameters (footprint, speed, and power) of SRAM and STT-RAM are given in TableI.…”

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confidence: 99%

A congestion-aware hybrid SRAM and STT-RAM buffer design for network-on-chip router

Lai

Cai

Jie

2023

IEICE Electron. Express

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Network-on-chip (NoC) offers a scalable and flexible communication infrastructure for many-cores systems. Buffers in router is used for fine-grain flow control and Quality of Service (QoS), yet it is the major contributor of area and power consumption. In this paper, we propose a hybrid buffer design with SRAM and Spin-Torque Transfer Magnetic RAM (STT-RAM) for NoC router leveraging a novel architecture combined Virtual Channel (VC) and Virtual Output Queuing (VOQ) to store congested and uncongested flow separately. Experiments demonstrates that the proposed scheme can achieve 11.8% network performance improvement and 32.9% power saving with only 8.2% area overhead degradation compared to conventional SRAM based buffer design.

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confidence: 99%