Hybrid overlay metrology for high order correction by using CDSEM

Leray, Philippe; Halder, Sandip; Lorusso, Gian; Baudemprez, Bart; Ito, Osamu; Okagawa, Yutaka

doi:10.1117/12.2222777

Cited by 3 publications

(4 citation statements)

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“…We have compared values of correction parameter between SEM-OL and Opt-OL in linear 10 correctable terms for intralayer (V0B to V0A) and interlayer (M1A to V0A). 39,40 The differences are not significant. Six parameters of CPE were compared between SEM-OL and optical IBO.…”

Section: (C)mentioning

confidence: 77%

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Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

Ito

Hasumi

2019

J. Micro/Nanolith. MEMS MOEMS

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Overlay control has been one of the most critical issues for manufacturing of leading edge semiconductor devices. Introduction of the double patterning process requires stringent overlay control. Conventional optical overlay (Opt-OL) metrology has technical challenges with measurement robustness, solving overlay discrepancy between overlay mark and device pattern, and measuring smaller marks laid out in large numbers within the die accurately for high-order correction. In contrast, scanning electron microscope-based overlay (SEM-OL) metrology can directly measure both overlay targets and actual devices or device-like structures on processed wafers with high spatial resolution. It can be used for reference metrology and optimization of Opt-OL measurement conditions. SEM-OL uses small structures, including actual device patterns, which allows insertion of many SEM-OL targets across a die. Precise overlay distribution can be measured using dedicated SEM-OL mark, improving measurement accuracy and repeatability. To extend SEM-OL capability, we have been developing SEM-OL techniques that can measure not only surface patterns by critical dimension SEM but also buried patterns for leading edge device processes. There are two techniques to detect buried patterns. One is to use high-acceleration voltage SEM, which detects backscattering electron emphasizing material contrast. It has been adopted for overlay measurements for memory and logic devices at after-etch inspection or even after-develop inspection. The other is to utilize charging effect, which reflects voltage contrast at the surface depending on the material properties of underneath structure. SEM-OL measurement using transient voltage contrast has been developed and its capability of overlay measurement has been proven. An overlay measurement algorithm using template matching method has been developed and was applied to dynamic random access memory (DRAM) process monitor in manufacturing. In order to extend SEM-OL metrology to beyond 3-nm node logic and cutting-edge DRAM devices (half pitch = 14 nm), we are improving measurement precision of detecting buried patterns and measurement throughput by developing optimized SEM-OL mark.

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Section: (C)mentioning

confidence: 77%

“…It was applied for improvement in R&D, Technology Ramp and for process monitor in manufacturing. 39,40 We will review SEM-OL metrology applied in current CD-SEM and high-voltage SEM (HV-SEM).…”

Section: Introductionmentioning

confidence: 99%

Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

Ito

Hasumi

2019

J. Micro/Nanolith. MEMS MOEMS

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“…With the continuous shrink in pattern size and increased density, overlay and edge-placement [13][14][15][16][17] control has become one of the most critical issues in semiconductor manufacturing. In particular, there is a clear need for SEMbased overlay measurements of after develop inspection (ADI) wafers, to serve as reference for optical overlay and make the necessary corrections before etching.…”

Section: Sem-based Overlay Measurement Between Resist and Buried Patt...mentioning

confidence: 99%

“…In addition, the overall size of these targets is relatively small (2 × 2 μm or less), thus allowing their in-chip placement. 13,14) In Fig. 1, we report SEM-based overlay measurements obtained using high voltage SEM.…”

Section: Sem-based Overlay Measurement Between Resist and Buried Patt...mentioning

confidence: 99%

Electron beam metrology for advanced technology nodes

Lorusso

Horiguchi

Bömmels

et al. 2019

Jpn. J. Appl. Phys.

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The critical dimension scanning electron microscope (CD-SEM) is one of the main tools used to estimate critical dimension (CD) in semiconductor manufacturing nowadays, but, as all metrology tools, it will face considerable challenges to keep up with the requirements of the future technology nodes. The root causes of these challenges are not uniquely related to the shrinking CD values, as one might expect, but to the increase in complexity of the devices in of morphology and chemical composition as well. In fact, complicated three-dimensional device architectures, high aspect ratio features, and wide variety of materials are some of the unavoidable characteristics of the future metrology nodes. In this paper, we report on the development of advanced CD-SEM metrology at imec on a variety of device platforms and processes, for both logics and memories. The large variety of results reported here a clear indication of the on-going creative effort needed to ensure that the critical potential of CD-SEM metrology tools is fully enabled for the 5 nm node and beyond.

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