Hybrid Partitioning Algorithm for Area Minimization in Circuits

Abstract

Area miniaturization is the essence of compaction of any application circuit in chip designing. The physical design stages involve virtual design realizations iterated for their efficiency. For this purpose, the CAD algorithms offer a variety of solutions depending on the needs and specifications of the designer. The use of EDA tools help in visualization of the effects of design algorithms on the circuit performance and the dimensions of the floor area occupied by the design. This paper demonstrates the effect of the hybrid algorithm on the circuit design. In this paper the effect of applying the move based partitioning algorithms KL,FM to circuitsand optimizing the cells of the circuit using Hybrid Genetic Algorithm (HGA) is discussed. The results suggest that, this approach on circuits provides scope to unify the stages of physical design stages of partitioning and placement and also optimize the area parameter of a physical design process.