Placement is a physical synthesis task that transforms a block/gate/transistor-level netlist into an actual layout for timing convergence. It is a crucial step that assembles the basic building blocks of logic netlist and establishes the overall timing characteristic of a design by determining exact locations of circuit elements within a given region. If a design is placed poorly, it is virtually impossible to close timing, no matter how much other physical synthesis and routing optimizations are applied to it. The algorithms for solving the mixed size placement problem fall into two categories, flat and hierarchical. The strategy of flat algorithm is to view both standard cells and macro blocks as the same placement components, whose advantage is that low complexity placement algorithm, such as quadratic-based algorithm, can be used to do the placement with very high speed. The strategy of hierarchical algorithm is to do the placement through block level and cell level, and the overlaps involving macro blocks are eliminated in block level. In both levels, the number of placement components reduces considerably.

Area miniaturization is the essence of compaction of any application circuit in chip designing. The physical design stages involve virtual design realizations iterated for their efficiency. For this purpose, the CAD algorithms offer a variety of solutions depending on the needs and specifications of the designer. The use of EDA tools help in visualization of the effects of design algorithms on the circuit performance and the dimensions of the floor area occupied by the design. This paper demonstrates the effect of the hybrid algorithm on the circuit design. In this paper the effect of applying the move based partitioning algorithms KL,FM to circuitsand optimizing the cells of the circuit using Hybrid Genetic Algorithm (HGA) is discussed. The results suggest that, this approach on circuits provides scope to unify the stages of physical design stages of partitioning and placement and also optimize the area parameter of a physical design process.

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