Hybrid Si/TMD 2D electronic double channels fabricated using solid CVD few-layer-MoS2 stacking for V<inf>th</inf> matching and CMOS-compatible 3DFETs

Abstract

Stackable 3DFETs such as FinFET using hybrid Si/ MoS 2 channels were developed using a fully CMOScompatible process. Adding several molecular layers (3-16 layers) of the transition-metal dichalcogenide (TMD), MoS 2 to Si fin and nanowire resulted in improved (+25%) I on,n of the FinFET and nanowire FET (NWFET). The PFETs also operated effectively and the N/P device V th are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics.I. Introduction 3DFETs can improve sub-20 nm CMOS node performance and substantially reduce supply voltage and short channel effects [1]. However, the traditional silicon channel must be replaced by high-mobility materials in future VLSI applications [2]-[3]. Heterogeneous twodimensional atomic crystals, namely, transition-metal dichalcogenide (TMD), have atomically smooth surface without dangling bounds and good mobility in CVD deposited films of atomic scale thickness are very attractive enablers of ultimately scaled transistors and 3D ICs [1,4]. However, a manufacturing flow must be realized using lowtemperature semiconductor process [5] and TMD by chemical vapor deposition (CVD) [6]. This paper presents the first CMOS process compatible TMD 3D transistor technology using novel hybrid Si/MoS 2 channel FinFET and NWFET with improved I on,n and matched V th of N and P devices. In comparison to previously published TMD transistors, this work reports the shortest gate length, thinnest gate dielectric, and first high performance at low voltage (Table 1 and Fig. 1). II. Process Integration and Device FabricationThe reported work made use of a previously published low temperature Tri-gate FinFETs technology [7]. The fewlayer MoS 2 growth step was inserted after blocking oxide deposition and clean (see Figs. 2 and Fig. 4 for FinFET and Fig. 3 and Fig. 5 and for NWFET). The ~5nm SiO 2 on the surface of the Si fin is responsible for setting the desirable low and matched V th of N and P devices as shown later. A low-temperature activation process that involved microwave annealing [5] was used after hybrid MoS 2 deposition. In Figs. 6 and 7, the TEM images show the hybrid Si/MoS 2 channel trigate FinFET and NWFET respectively. Few-layer MoS 2 was successfully integrated into 3DFETs technology using low-temperature CVD with the number of MoS 2 layers determined by deposition duration (Figs. 8 and 9). The TiN gate over the hybrid Si/MoS 2 fins is 50 nm long (Fig. 10). III. Results and Discussion A. MoS 2 Material AnalysisMoS 2 material analysis was performed over flat regions of the wafer and over the hybrid Si/MoS 2 fins. Figs. 11(a) and (b) show the S L-edge and Mo M-edge features of the MoS 2 clearly observed for both the films deposited on the flat Si substrate and over the hybrid Si/MoS 2 fins using X-ray absorption spectroscopy. Fig. 12 shows the X-ray absorption near the edge spectrum, which revealed that the Mo M-edge spectrum exhibited a peak in films deposited on flat Si substrate and on the hybrid Si/MoS 2 channel. Strong separated features ...

A FinFET with one atomic layer channel

“…4c we plot the iterative progresses of FinFETs as a function of time line. It is seen that, strikingly, the W fin has been levelling off since 2 decades 4,6,10,11,18,[22][23][24][25][26][27][28] . Our present work brings this nanostructure to a limit of 0.6 nm ML, an order of magnitude thinner than the W fin of state-of-the-art FinFETs.…”

Analyzing the Carrier Mobility in Transition‐Metal Dichalcogenide MoS2 Field‐Effect Transistors

“…In 2014, a 3D FET with MoS 2 channel covering HfO 2 /Si upstanding Fin structure was demostrated. Low operating voltage down to 1 V and matched V th between the n‐type and p‐type transport regime were realized in the hybrid Si/TMDC FETs with 50 nm channel length and equivalent oxide thickness (EOT) <1 nm . More recently, Chen et al demonstrated an ultra‐scaled U‐shape MoS 2 transistor with self‐aligned Si source/drain and Si topgate (Figure b,c), by a fully CMOS‐compatible process.…”

Remarkably high mobility ultra-thin-film metal-oxide transistor with strongly overlapped orbitals

“…To reach high mobility, epitaxial growth of crystalline MoS 2 on a crystal substrate is needed. Unfortunately, the mobility is lower for CVD-grown MoS 2 25 26 27 28 than peeled-off flakes from crystals 21 22 23 24 25 26 27 28 . The lattice mismatch caused defects are the other major concern for circuit yield.…”

“…This TFT also showed a high I ON /I OFF of 2.3 × 10 7 , low sub-threshold swing ( SS ) of 0.11 V/decade, low threshold voltage ( V T ) of 0.27 V, low drive voltage of 2.5 V for low switching power, and ultra-thin layer with a thickness of 4.5 nm. Such ultra-thin thickness is comparable with that of multilayered MoS 2 27 for low DC standby power consumption. Notably, Sn (Group IV) has ns 2 np 2 electron configuration and directive sp 3 orbitals, which differ from those of Zn 7 .…”

“…Alternatively, high mobility, high transistor on-current ( I ON ), and low off-current ( I OFF ) TFTs are found in two-dimensional metal-chalcogenide 21 22 23 24 25 26 27 28 . However, chemical vapor deposition (CVD)-grown MoS 2 25 26 27 28 shows a considerably lower mobility compared with peeled-off flakes from crystals 21 . To further increase the display pixel density and drive organic light-emitting diodes (OLED), higher mobility and I ON than those of ZnO-based TFTs are needed.…”