Hybrid topology of symmetrical multilevel inverter using less number of devices

Abstract

The interest in development of newer topologies of multilevel inverter has been increasing rapidly in past few years. Recently introduced topologies achieve higher number of output voltage steps with reduced number of switches, DC voltage sources, voltage stress across switches and losses as compared with the conventional topologies. In this study, a new structure of symmetrical multilevel inverter is proposed. The proposed structure offers reduced number of controlled switches, power diodes and DC sources as compared with classical and recently proposed topologies in the literature. Reduction of switch count and DC voltage sources reduces the size, cost, complexity and enhances overall performance. Proposed topology is capable of producing 7, 9 and 11 levels of output voltage with seven switches only. Moreover, significant reduction in voltage stress across the switches can be achieved. A comparative analysis of proposed topology with the conventional topology and recently published topologies has been made in terms of controlled switches, power diodes, driver circuit requirement, DC voltage sources and blocking voltage. Multi-carrier pulse-width modulation strategy is adopted for generating the switching pulses. Simulation study of the proposed topology has been carried out using Matlab/Simulink and feasibility of topology has been validated experimentally.

A new hybrid flying capacitor–based single‐phase nine‐level inverter

“…It can be noted that the complexity in the implementation of the proposed circuit is less because of a lower component count compared with conventional and other recent topologies in previous studies . Moreover, for the same number of output voltage levels, the number of V dc ‐rated switches required in the proposed topology are less by 62.5% and 25% compared with Gautam et al and Sandeep and Udaykumar, respectively. The FC voltage ripple is more in Sandeep and Udaykumar and Vahedi et al because of the reduced number of redundant switching states.…”

“…Existing nine‐level hybrid inverters: A, Li et al; B, Odeh and Nnadi; C, Gautam et al; D, Sandeep and Udaykumar; E, Sandeep and Udaykumar; and F, Sandeep and Udaykumar…”

A new and generalized structure of single‐phase and three‐phase cascaded multilevel inverter with reduced power components

“…Thus, it is always preferable to obtain a greater number of output voltage levels with a much lesser number of power semi‐conductor devices, thereby reducing the complexity and enhancing the reliability of the converter. Recently, several reduced switch MLI configurations are developed by the researchers to enhance the voltage levels with lesser number of power semi‐conductor switches …”

“…A charge balance control scheme‐based MLI is presented in Gupta and Jain . The symmetrical value of DC sources for a hybrid MLI topology is proposed in Gautam et al The topologies put forward in Alishah et al and Hinago and Koizumi have been organized in a fashion such that it can be operated for both the symmetrical and asymmetrical configurations. A switched‐diode MLI is revealed in Alishah et al experiences a spike in output voltage and thereby disturbing the power quality of the inverter.…”

Multilevel Inverter Topology with Modified Pulse Width Modulation and Reduced Switch Count

“…Based on the magnitude of these isolated DC voltage sources, CHB MLI has been classified as symmetric and asymmetric [9]. In symmetric type inverter, the magnitudes of DC sources are equal which offers superior modularity, whereas the magnitude of DC voltage sources are not equal in the asymmetric type inverter [10]. It is possible to achieve higher number of output levels during asymmetric operation as compared with symmetric operation for the same amount of switches and DC sources.…”