Hybridization of NSGA-II with greedy re-assignment for variation tolerant logic mapping on nano-scale crossbar architectures

Zhong, Fugui; Yuan, Bo; Li, Bin

doi:10.1145/2598394.2598430

Cited by 2 publications

(6 citation statements)

References 4 publications

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“…We see that the proposed technique always gives the best result, which is 3-5% better than greedy from the literature [20] and 10-15% than random mapping. The reason is that the greedy mapping proposed in [20], and also used in [22], determines lb i 's by using sums of all delay values in a V M column. However, we select a minimum sum of T i delay values where T i is the number of 1's in the F M column to be mapped.…”

Section: Simulations For Vtlmmentioning

confidence: 75%

“…In average, runtimes are generally much higher (×30 − 40) than ours. In order to improve runtimes, Zhong et al use a greedy reassignment technique [20], originally proposed in [21]. We also used this method as as an alternative to initial column mapping method and compared optimization results.…”

Section: Previous Workmentioning

confidence: 99%

“…We evaluate the proposed initial column mapping technique by comparing it with random mapping and greedy mapping method proposed in [20]; all of these methods are used with our hill climbing algorithm. Randomly generated benchmarks with different sizes are used for a fair comparison.…”

Section: Simulations For Vtlmmentioning

confidence: 99%

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A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays

Peker

Altun

2018

IEEE Trans. Multi-Scale Comp. Syst.

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Nano-crossbar arrays are area and power efficient structures, generally realized with self-assembly based bottom-up fabrication methods as opposed to relatively costly traditional top-down lithography techniques. This advantage comes with a price: very high process variations. In this work, we focus on the worst-case delay optimization problem in the presence of high process variations. As a variation tolerant logic mapping scheme, a fast hill climbing algorithm is proposed; it offers similar or better delay improvements with much smaller runtimes compared to the methods in the literature. Our algorithm first performs a reducing operation for the crossbar motivated by the fact that the whole crossbar is not necessarily needed for the problem. This significantly decreases the computational load up to 72% percent for benchmark functions. Next, initial column mapping is applied. After the first two steps that can be considered as preparatory, the algorithm proceeds to the last step of hill climbing row search with column reordering where optimization for variation tolerance is performed. As an extension to this work, we directly apply our hill climbing algorithm on defective arrays to perform both defect and variation tolerance. Again, simulation results approve the speed of our algorithm, up to 600 times higher compared to the related algorithms in the literature without sacrificing defect and variation tolerance performance.

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Section: Simulations For Vtlmmentioning

confidence: 75%

Section: Previous Workmentioning

confidence: 99%

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A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays

Peker

Altun

2018

IEEE Trans. Multi-Scale Comp. Syst.

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“…This paper proposes one such operator, called defect-and variationaware local search (D/VALS). The key idea is inherited from the greedy reassignment (GR) local search operators for DTLM [18] and VTLM [21], which is to reassign the values of parts of the individual by taking advantage of the greedy information extracted from the problems. However, instead of individually utilizing defect information [18] or variation information [21], the D/VALS operator is capable of utilizing the combined information of both defect and variation.…”

Section: Take Down Policymentioning

confidence: 99%

“…Given a parent chromosome, the operator produces a child chromosome that is expected to outperform the parent. The key idea of the operator is inherited from the previous GR local search operators for DTLM [18] and VTLM [21]. However, instead of individually utilizing defect information [18] or variation information [21], the operator is capable of utilizing the combined information on both defect and variation.…”

Section: Defect/variation-aware Local Searchmentioning

confidence: 99%

Defect- and Variation-Tolerant Logic Mapping in Nanocrossbar Using Bipartite Matching and Memetic Algorithm

Yuan

Chen

et al. 2016

IEEE Trans. VLSI Syst.

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High defect density and extreme parameter variation make it very difficult to implement reliable logic functions in crossbar-based nanoarchitectures. It is a major design challenge to tolerate defects and variations simultaneously for such architectures. In this paper, a method based on a bipartite matching and memetic algorithm is proposed for defect-and variation-tolerant logic mapping (D/VTLM) problem in crossbarbased nanoarchitectures. In the proposed method, the search space of the D/VTLM problem can be dramatically reduced through the introduction of the min-max weight maximumbipartite-matching (MMW-MBM) and a related heuristic bipartite matching method. MMW-MBM is defined on a weighted bipartite graph as an MBM, where the maximal weight of the edges in the matching has a minimal value. In addition, a defect-and variation-aware local search (D/VALS) operator is proposed for D/VTLM and embedded in a global search framework. The D/VALS operator is able to utilize the domain knowledge extracted from problem instances and, thus, has the potential to search the solution space more efficiently. Compared with the state-of-the-art heuristic and recursive algorithms, and a simulated annealing algorithm, the good performance of our proposed method is verified on a 3-bit adder and a large set of random benchmarks of various scales.

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Hybridization of NSGA-II with greedy re-assignment for variation tolerant logic mapping on nano-scale crossbar architectures

Cited by 2 publications

References 4 publications

A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays

A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays

Defect- and Variation-Tolerant Logic Mapping in Nanocrossbar Using Bipartite Matching and Memetic Algorithm

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