HyCUBE

Karunaratne, Manupa; Mohite, Aditi Kulkarni; Mitra, Tulika; Peh, Li-Shiuan

doi:10.1145/3061639.3062262

Cited by 132 publications

(22 citation statements)

References 7 publications

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“…An important property of previously proposed CGRAs (e.g. [5]- [8]) is the notion of multiple contexts. A context is a single configuration of the CGRA's logic functionality and routing connectivity.…”

Section: B Multi-context Cgrasmentioning

confidence: 99%

“…In CGRAs, the small number of input ports on a ALU (usually 2) means that every processing element can have a fully-connected crossbar -even in CGRAs with up to 8 PE inputs [6] (ADRES) or very flexible routing [8] (HyCUBE). As a prototypical example, consider the orthogonally-connected CGRA in Fig.…”

Section: A Connectivitymentioning

confidence: 99%

“…Each cluster also has one memory port and one IO port. HyCUBE[8] Arch. A homogeneous array of PEs, each associated with a fully-connected crossbar which are connected in a grid.…”

mentioning

confidence: 99%

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Generic Connectivity-Based CGRA Mapping via Integer Linear Programming

Walker

Anderson

2019

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

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Coarse-grained reconfigurable architectures (CGRAs) are programmable logic devices with large coarsegrained ALU-like logic blocks, and multi-bit datapath-style routing. CGRAs often have relatively restricted data routing networks, so they attract CAD mapping tools that use exact methods, such as Integer Linear Programming (ILP). However, tools that target general architectures must use large constraint systems to fully describe an architecture's flexibility, resulting in lengthy run-times. In this paper, we propose to derive connectivity information from an otherwise generic device model, and use this to create simpler ILPs, which we combine in an iterative schedule and retain most of the exactness of a fully-generic ILP approach. This new approach has a speed-up geometric mean of 5.88× when considering benchmarks that do not hit a time-limit of 7.5 hours on the fully-generic ILP, and 37.6× otherwise. This was measured using the set of benchmarks used to originally evaluate the fully-generic approach and several more benchmarks representing computation tasks, over three different CGRA architectures. All run-times of the new approach are less than 20 minutes, with 90th percentile time of 410 seconds. The proposed mapping techniques are integrated into, and evaluated using the open-source CGRA-ME architecture modelling and exploration framework [1].

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Section: B Multi-context Cgrasmentioning

confidence: 99%

Section: A Connectivitymentioning

confidence: 99%

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Generic Connectivity-Based CGRA Mapping via Integer Linear Programming

Walker

Anderson

2019

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

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“…CGRA is known to be more efficient than FPGA in terms of reconfigurability in computation and interconnection resources [1]. During recent decades, many CGRAs [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18] have been proposed with different reconfigure schemes. Wijtvliet et al [19] classified the reconfigure schemes into coarse and fine temporal reconfiguration granularities.…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, we focus on modulo-scheduled CGRAs, a class of fine-grained temporal reconfiguration CGRAs that is capable of executing diverse loop kernels in softwarepipelining scheme [8][9][10]13,18,20]. In general, the modulo-scheduled CGRAs (Figure 1) consist of a processing element array (PEA), on-chip global context memory (GCM) and onchip multi-bank shared data memory (SDM).…”

Section: Introductionmentioning

confidence: 99%

Similarity-Aware Architecture/Compiler Co-Designed Context-Reduction Framework for Modulo-Scheduled CGRA

Zhao

Sheng

et al. 2021

Electronics

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Modulo-scheduled coarse-grained reconfigurable array (CGRA) processors have shown their potential for exploiting loop-level parallelism at high energy efficiency. However, these CGRAs need frequent reconfiguration during their execution, which makes them suffer from large area and power overhead for context memory and context-fetching. To tackle this challenge, this paper uses an architecture/compiler co-designed method for context reduction. From an architecture perspective, we carefully partition the context into several subsections and only fetch the subsections that are different to the former context word whenever fetching the new context. We package each different subsection with an opcode and index value to formulate a context-fetching primitive (CFP) and explore the hardware design space by providing the centralized and distributed CFP-fetching CGRA to support this CFP-based context-fetching scheme. From the software side, we develop a similarity-aware tuning algorithm and integrate it into state-of-the-art modulo scheduling and memory access conflict optimization algorithms. The whole compilation flow can efficiently improve the similarities between contexts in each PE for the purpose of reducing both context-fetching latency and context footprint. Experimental results show that our HW/SW co-designed framework can improve the area efficiency and energy efficiency to at most 34% and 21% higher with only 2% performance overhead.

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