HyCUBE: A 0.9V 26.4 MOPS/mW, 290 pJ/op, Power Efficient Accelerator for IoT Applications

Wang, Bo; Karunarathne, M. Sajeewani; Kulkarni, Aditi; Mitra, Tulika; Peh, Li-Shiuan

doi:10.1109/a-sscc47793.2019.9056954

Cited by 26 publications

(5 citation statements)

References 8 publications

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“…Each PE has a local register file for storage of intermediate results and configuration memory. The PEs are placed in a grid and communicate with only the immediate neighbors using ALU MOV 5b closely resembles HyCUBE [19,38]. It has a full-fledged ALU just like HM-ADRES.…”

Section: Quantifying Inefficiency Of Homogeneous Cgrasmentioning

confidence: 99%

“…Several academic CGRA architectures have been proposed in recent years, such as ADRES [26], Morphosys [36], HyCUBE [19,38], and commercial ones like Samsung Reconfigurable Processor (SRP) [21], Wave DPU [27], DRP [13] and Plasticine [32]. Most existing CGRAs (e.g., SRP [21], Morphosys [36], ADRES [26]) adopt a regular structure where identical PEs and memory are connected with a uniform network.…”

Section: Introductionmentioning

confidence: 99%

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REVAMP: a systematic framework for heterogeneous CGRA realization

Bandara

Wijerathne

Mitra

et al. 2022

Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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Coarse-Grained Reconfigurable Architectures (CGRAs) provide an excellent balance between performance, energy efficiency, and flexibility. However, increasingly sophisticated applications, especially on the edge devices, demand even better energy efficiency for longer battery life.Most CGRAs adhere to a canonical structure where a homogeneous set of processing elements and memories communicate through a regular interconnect due to the simplicity of the design. Unfortunately, the homogeneity leads to substantial idle resources while mapping irregular applications and creates inefficiency. We plan to mitigate the inefficiency by systematically and judiciously introducing heterogeneity in CGRAs in tandem with appropriate compiler support.We propose REVAMP, an automated design space exploration framework that helps architects uncover and add pertinent heterogeneity to a diverse range of originally homogeneous CGRAs when fed with a suite of target applications. REVAMP explores a comprehensive set of optimizations encompassing compute, network, and memory heterogeneity, thereby converting a uniform CGRA into a more irregular architecture with improved energy efficiency. As CGRAs are inherently software scheduled, any micro-architectural optimizations need to be partnered with corresponding compiler support, which is challenging with heterogeneity. The REVAMP framework extends compiler support for efficient mapping of loop kernels on the derived heterogeneous CGRA architectures.We showcase REVAMP on three state-of-the-art homogeneous CGRAs, demonstrating how REVAMP derives a heterogeneous variant of each homogeneous architecture, with its corresponding compiler optimizations. Our results show that the derived heterogeneous architectures achieve up to 52.4% power reduction, 38.1% area reduction, and 36% average energy reduction over the corresponding homogeneous versions with minimal performance impact for the selected kernel suite.

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Section: Quantifying Inefficiency Of Homogeneous Cgrasmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

REVAMP: a systematic framework for heterogeneous CGRA realization

Bandara

Wijerathne

Mitra

et al. 2022

Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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“…1, eliminate complex instruction pipeline and centralized communication to achieve high energy efficiency [7,32]. In recent years, Miscellaneous RSAs have begun to emerge as domain-specific accelerators such as Eyeriss [7] and FlexFlow [35] for artificial intelligence (AI) applications, Darwin-WGA [51] for genome alignments workloads, and HyCUBE [54] for internet of things (IOT). These architectures differ a lot in PE organization, interconnection topology, etc., because architects typically perform domain-specific design space exploration in the dimensions shown in…”

Section: Background and Motivation 21 Reconfigurable Spatial Architec...mentioning

confidence: 99%

“…There are four kinds of interconnection patterns existing in the current RSA design: mesh-like, crossbar, point-to-point, and bus. We focus on the most popular mesh-like RSAs (e.g., [33,38,47]) and crossbarbased (X-bar) RSAs (e.g., [14,20,43,54,56]) because of their good scalability and high energy efficiency [58]. It is noteworthy that mesh-plus, depopulated crossbar/mesh, hierarchical interconnections are all supported because CUs are clustered according to distances and other structure-neutral metrics.…”

Section: 𝑂𝑝𝑠 𝑖mentioning

confidence: 99%

“…With the combination of these strategies, CaSMap has higher success rate (consequently less iterations) and performance. • We implemented and evaluated CaSMap for classic and latest RSA topologies: MorphoSys [47], HReA [33], HyCUBE [54], and REVEL [56]. The quality of mapping and the scalability of software/hardware are compared with the state-of-the-art systematic backtracking method.…”

Section: Introductionmentioning

confidence: 99%

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CaSMap

Man

Zhu

Song

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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Today, reconfigurable spatial architectures (RSAs) have sprung up as accelerators for compute-and data-intensive domains because they deliver energy and area efficiency close to ASICs and still retain sufficient programmability to keep the development cost low. The mapper, which is responsible for mapping algorithms onto RSAs, favors a systematic backtracking methodology because of high portability for evolving RSA designs. However, exponentially scaling compilation time has become the major obstacle. The key observation of this paper is that the key limiting factor to the systematic backtracking mappers is the waterfall mapping model which resolves all mapping variables and constraints at the same time using single-level intermediate representations (IRs).This work proposes CaSMap, an agile mapper framework independent of software and hardware of RSAs. By clustering the lowest-level software and hardware IRs into multi-level IRs, the original mapping process can be scattered as multi-stage decomposed ones and therefore the mapping problem with exponential complexity is mitigated. This paper introduces (a) strategies for clustering low-level hardware and software IRs with static connectivity and critical path analysis. (b) a multi-level scattered mapping model in which the higher-level model carries out the heuristics from IR clustering, endeavors to promote mapping success rate, and reduces the scale of the lower-level model. Our evaluation shows that CaSMap is able to reduce the problem scale (nonzeros) by 80.5% (23.1%-94.9%) and achieve a mapping time speedup of 83× over the state-of-the-art waterfall mapper across four different RSA topologies: MorphoSys, HReA, HyCUBE, and REVEL. CCS CONCEPTS• Computer systems organization → Reconfigurable computing; • Software and its engineering → Retargetable compilers.

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