Hypergraph partitioning for VLSI CAD: methodology for heuristic development, experimentation and reporting

Abstract

We illustrate how technical contributions in the VLSI CAD partitioning literature can fail to provide one or more of: (i) reproducible results and descriptions, (ii) an enabling account of the key understanding or insight behind a given contribution, and (iii) experimental evidence that is not only contrasted with the state-of-the-art, but also meaningful in light of the driving application. Such failings can lead to reporting of spurious and misguided conclusions. For example, new ideas may appear promising in the context of a weak experimental testbed, but in reality do not advance the state of the art. The resulting inefficiencies can be detrimental to the entire research community. We draw on several models (chiefly from the metaheuristics community) [5] for experimental research and reporting in the area of heuristics for hard problems, and suggest that such practices can be adopted within the VLSI CAD community. Our focus is on hypergraph partitioning.

Reporting of standard cell placement results

“…For example, the delay reported in [16] is a factor of 10 lower than the result of [20]. Other areas of VLSI CAD research are likely to have similar problems: [2] focused on hypergraph partitioning, and makes a number of suggestions which could very easily apply here. As fabrication technology advances, and the size of the "design gap" increases, improvements to the reporting and evaluation of results becomes increasingly important.…”

“…As with [2], we observe that the lack of consensus on interpretations hampers placement research. In many published works, there are unintentional comparisons of "apples" to "oranges," resulting in incorrect or misleading conclusions.…”

“…Contrary to what might be anticipated for a problem this well studied, there are few "common assumptions." This paper has a motivation similar to that of [2], which illustrated difficulties in hypergraph partitioning research, due to variation in implementation of "standard" algorithms. The challenges faced with circuit placement are substantially more difficult than those observed with hypergraph partitioning: there is not even agreement on how a result should be measured, to say nothing of how a Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.…”

Hypergraph Partitioning and Clustering

“…Techniques for evaluating partitioning heuristics and experiments using these benchmarks were given in [17]. Examples of such comparisons between hMETIS and MLPart are found in [16].…”

“…CLIP is used in FM also tends to have problems when the highest-gain move is a vertex with high weight that cannot move across the cutline due to balance constraints. This is known as the corking effect and some techniques for handling it are presented in [17]. Techniques specific to hypergraphs with fixed vertices are presented in [16].…”