The facility layout problem is concerned with the arrangement of a given number of rectangular facilities so as to minimize the total cost associated with the (known or projected) interactions between them. We consider the one-dimensional space-allocation problem (ODSAP), also known as the single-row facility layout problem, which consists in finding an optimal linear placement of facilities with varying dimensions on a straight line. We construct a semidefinite programming (SDP) relaxation providing a lower bound on the optimal value of the ODSAP. To the best of our knowledge, this is the first non-trivial global lower bound for the ODSAP in the published literature. This SDP approach implicitly takes into account the natural symmetry of the problem and, unlike other algorithms in the literature, does not require the use of any explicit symmetry-breaking constraints. Furthermore, the structure of the SDP relaxation suggests a simple heuristic procedure which extracts a feasible solution to the ODSAP from the optimal matrix solution to the SDP relaxation. Computational results show that this heuristic yields a solution which is consistently within a few percentage points of the global optimal solution.

Ana/ytic placement methods that simultaneously minimize wire length and spread cells are receiving renewed attention from both academia and industiy In this paper we describe the implementation details of a force-directed placer: FDP. Specifically, we provide (I) a description of eficient force computation for spreading cells, (2) an illustration of numerical instability in these methods and a meam by which these instabilities are avoided, (3) spread metrics for measuring cell distribution throughout the placement region and (4) a complementary technique which aids in directly minimizing HPWL. We present results comparing our ana/ytic placer to other academic tools for both standard cell and mixed-size designs. Compared to Kraftwerk and Capo 8.7, our tool produces results with an average improvement of 9% and 3%, respectively

We illustrate how technical contributions in the VLSI CAD partitioning literature can fail to provide one or more of: (i) reproducible results and descriptions, (ii) an enabling account of the key understanding or insight behind a given contribution, and (iii) experimental evidence that is not only contrasted with the state-of-the-art, but also meaningful in light of the driving application. Such failings can lead to reporting of spurious and misguided conclusions. For example, new ideas may appear promising in the context of a weak experimental testbed, but in reality do not advance the state of the art. The resulting inefficiencies can be detrimental to the entire research community. We draw on several models (chiefly from the metaheuristics community) [5] for experimental research and reporting in the area of heuristics for hard problems, and suggest that such practices can be adopted within the VLSI CAD community. Our focus is on hypergraph partitioning.

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