Hypernode reduction modulo scheduling

Llosa, Josep; Valero, Mateo; Ayguad, Eduard; González, Antonio

doi:10.1109/micro.1995.476844

Cited by 43 publications

(33 citation statements)

References 16 publications

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“…Modulo scheduling is a class of software pipelining algorithms that was proposed at the begining of last decade [24] and has been incorporated into some product compilers (e.g., [22], [7]). Besides, many research papers have recently appeared on this topic [11], [14], [26], [13], [29], [12], [27], [23], [30], [18].…”

Section: Introductionmentioning

confidence: 99%

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Modulo scheduling with reduced register pressure

Llosa

Valero

Agyuade

et al. 1998

IEEE Trans. Comput.

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Abstract-Software pipelining is a scheduling technique that is used by some product compilers in order to expose more instruction level parallelism out of innermost loops. Modulo scheduling refers to a class of algorithms for software pipelining. Most previous research on modulo scheduling has focused on reducing the number of cycles between the initiation of consecutive iterations (which is termed II) but has not considered the effect of the register pressure of the produced schedules. The register pressure increases as the instruction level parallelism increases. When the register requirements of a schedule are higher than the available number of registers, the loop must be rescheduled perhaps with a higher II. Therefore, the register pressure has an important impact on the performance of a schedule. This paper presents a novel heuristic modulo scheduling strategy that tries to generate schedules with the lowest II, and, from all the possible schedules with such II, it tries to select that with the lowest register requirements. The proposed method has been implemented in an experimental compiler and has been tested for the Perfect Club benchmarks. The results show that the proposed method achieves an optimal II for at least 97.5 percent of the loops and its compilation time is comparable to a conventional top-down approach, whereas the register requirements are lower. In addition, the proposed method is compared with some other existing methods. The results indicate that the proposed method performs better than other heuristic methods and almost as well as linear programming methods, which obtain optimal solutions but are impractical for product compilers because their computing cost grows exponentially with the number of operations in the loop body.

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Section: Introductionmentioning

confidence: 99%

“…The ordering phase orders 1. A preliminary version of this work appeared in [18]. the nodes before scheduling them, so that only predecessors or successors of a node can be scheduled before it is scheduled (except for recurrences), reducing the register requirements.…”

Section: Introductionmentioning

confidence: 99%

Modulo scheduling with reduced register pressure

Llosa

Valero

Agyuade

et al. 1998

IEEE Trans. Comput.

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“…The iterative approach presented in this paper first preorders the nodes in what we call the PriorityList, using HRMS strategy [22]. After that the actual iterative scheduling process constructs a Partial Schedule S by scheduling nodes one at a time following the order in the PriorityList.…”

Section: Definitions and Conceptsmentioning

confidence: 99%

“…Most of the early modulo scheduling techniques focused mainly on achieving high throughput [l, 7,25, 281. However, one of the drawbacks of modulo scheduling (and software pipelining in general) is that they increasc: the register requirements. This has motivated some recent modulo scheduling approaches that not only try to maximize throughput but also try to minimize register requirements [6,9,16,20,22]. Despite obtaining schedules with reduced register requirements, if a schedule requires more registers than those available in the processor some additional steps are needed such as an increase in the initiation interval (11) [21], the addition of spill code and rescheduling of the loop [21] or a combination of all of these [32].…”

Section: Introductionmentioning

confidence: 99%

Modulo scheduling with integrated register spilling for clustered VLIW architectures

Zalamea¹,

Llosa²,

Ayguadé³

et al.

Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture. MICRO-34

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“…Our workbench is composed of 1180 loops that account for 78% of the execution time of the Perfect Club [3]. The loops have been obtained using the experimental tool Ictíneo [2] and software pipelined using Hypernode Reduction Modulo Scheduling [15,16], a register pressure sensitive heuristic that achieves near optimal schedules. Register allocation has been performed using the wands-only strategy and the end-fit with adjacency ordering [22].…”

Section: Introductionmentioning

confidence: 99%