Modulo scheduling with reduced register pressure

Abstract

Abstract-Software pipelining is a scheduling technique that is used by some product compilers in order to expose more instruction level parallelism out of innermost loops. Modulo scheduling refers to a class of algorithms for software pipelining. Most previous research on modulo scheduling has focused on reducing the number of cycles between the initiation of consecutive iterations (which is termed II) but has not considered the effect of the register pressure of the produced schedules. The register pressure increases as the instruction level parallelism increases. When the register requirements of a schedule are higher than the available number of registers, the loop must be rescheduled perhaps with a higher II. Therefore, the register pressure has an important impact on the performance of a schedule. This paper presents a novel heuristic modulo scheduling strategy that tries to generate schedules with the lowest II, and, from all the possible schedules with such II, it tries to select that with the lowest register requirements. The proposed method has been implemented in an experimental compiler and has been tested for the Perfect Club benchmarks. The results show that the proposed method achieves an optimal II for at least 97.5 percent of the loops and its compilation time is comparable to a conventional top-down approach, whereas the register requirements are lower. In addition, the proposed method is compared with some other existing methods. The results indicate that the proposed method performs better than other heuristic methods and almost as well as linear programming methods, which obtain optimal solutions but are impractical for product compilers because their computing cost grows exponentially with the number of operations in the loop body.

Compiler optimization-space exploration

“…Heuristics that try to avoid register spilling due to overly aggressive software pipelining have been proposed [10,11]. Despite their efforts, the authors describe a range of cases where their heuristics fail to make the best decision.…”

A standard task graph set for fair evaluation of multiprocessor scheduling algorithms

“…The performance of scheduling algorithms has been evaluated using randomly generated task graphs [4-6, 15, 17-19, 22-24] or task graphs modelled from a few application programs [6,16,17,[20][21][22][25][26][27]]. However, these task graphs are not typically available to other researchers.…”

Exploiting pseudo-schedules to guide data dependence graph partitioning

“…High register bus pressure caused by inter-cluster communications and high register pressure (i.e., many operands live concurrently) can dramatically increase the Á Á [26]. In this work we look to provide an scheduling approach that addresses all the above issues, exposing instruction-level parallelism while reducing register pressure, register bus pressure, and functional unit pressure.…”

“…For this reason, many heuristics have been proposed in an attempt to find near-optimal schedules. The objectives of past heuristicbased approaches have had different goals: increasing throughput [20,32], minimizing register pressure [9,8], reducing the effect of the cache misses, or improving several objectives simultaneously [8,19,26,34]. All of these studies focused on modulo scheduling algorithms targeting unified (i.e., non-partitioned) architectures.…”