<i>In-Situ</i> Timing Monitor-Based Adaptive Voltage Scaling System for Wide-Voltage-Range Applications

Shan, Weiwei; Shi, Longxing

doi:10.1109/access.2017.2670644

Cited by 15 publications

(9 citation statements)

References 24 publications

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“…14 In addition, aging and IRF 15 can cause timing violations in the data path. In situ on-line monitoring techniques have been used for timing error detection and correction at the critical paths, 11 timing slack measurement, 13 adaptive voltage scaling 16 and aging detection. 17 With some modi¯cations, the in situ on-line monitoring techniques can be used for IRF detection at the chip levels as well.…”

Section: To Monitor Degradation In Connectorsmentioning

confidence: 99%

A Digital On-Line Monitor for Detecting Intermittent Resistance Faults at Board Level

Ebrahimi

Kerkhoff

2019

J CIRCUIT SYST COMP

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The reliability of board-level data communications intensively depends on the reliability of interconnections on a board. One of the most challenging interconnections reliability threats is intermittent resistive faults (IRFs). Detecting such faults is a major challenge. The main reason is the random behavior of these faults. They may occur randomly in time, duration and amplitude. The occurrence rate can vary from a few nanoseconds to months. This paper investigates IRF detection at the board level by introducing a new digital in situ IRF monitor. Hardware-based fault injection has been used to validate the proposed IRF monitor. As case studies, two widely used on-board transmission protocols namely the Universal Asynchronous Receiver Transmitter (UART) and the Serial Peripheral Interface bus (SPI), have been used. In addition, one fault management framework, based on the IJTAG standard, has been implemented to collect and characterize information from the monitors. The experimental results show that the proposed monitor is effective in detecting IRFs at the board level.

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Section: To Monitor Degradation In Connectorsmentioning

confidence: 99%

A Digital On-Line Monitor for Detecting Intermittent Resistance Faults at Board Level

Ebrahimi

Kerkhoff

2019

J CIRCUIT SYST COMP

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“…The impact of the PVT variations in CMOS circuits increase with the technology scaling, making reliability among the most important challenges facing nanoscale system design. Adaptive solutions have been proposed to minimize the performance lost due to PVT variations, allowing systems to tolerate worst-case scenarios by reducing the delay and power impact under normal operation [1][2][3][4][5][6][7][8]. For adaptive methodologies, voltage, frequency, current, power, and activity monitors are used to control the circuit behavior or performance [9][10][11].…”

Section: Introductionmentioning

confidence: 99%

Delay Based Auto-Calibrated PVT Monitor System and Method

Giron¹,

Martínez²,

Avendano³

2020

CSSP

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In this paper, an auto-calibrated PVT (process, voltage, temperature) monitoring system based on delay chains and flip-flops is presented. The system and method are proposed to be used by IP's (Intellectual property) that require to monitor PVT conditions during its operation and depending on the detected changes be configurable or adaptive. The methodology is based on embedded PVT monitors that sense when the propagation delay variation in standard cells reaches a certain threshold. The system implementation is intended to be done since the RTL (register transfer level) design stage to avoid or reduce the full custom design effort. The PVT monitors are built using buffers from a technology design kit. The information of the PVT monitors is sent to a logic module that calibrates the monitors to choose the best monitoring option depending on the PVT corner, available clock, and standard cells delay. The system includes also a logic module that collects and sends the data inside or outside the chip, in parallel or serial modes. Characterization results of the PVT monitors are presented including different delay chains, and clock combinations trough different PVT corners. This system is intended to detect the change of the propagation delay in the cells due to the PVT conditions combined, and not to provide the stand-alone value of voltage, temperature, or process. Otherwise, one of the reasons for this proposal is to avoid the use of individual sensors.

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“…Since large-magnitude VDD droops rarely occur, the reserved voltage margin limits the performance and energy efficiency. Several adaptive circuit techniques [3][4][5][6][7][8][9][10] have been proposed to reduce the effect of VDD droops by sensing the VDD variation and adjusting the clock. The adaptive clocking system [4] eliminated the response-time limitation by selecting the delay-locked loop (DLL) clock output to adjust the clock.…”

Section: Introductionmentioning

confidence: 99%

Low Overhead and Fast Reaction Adaptive Clocking System for Voltage Droop Tolerance

Shang

Shan

Xiang³

et al. 2019

Chin. j. electron.

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In-Situ Timing Monitor-Based Adaptive Voltage Scaling System for Wide-Voltage-Range Applications

Cited by 15 publications

References 24 publications

A Digital On-Line Monitor for Detecting Intermittent Resistance Faults at Board Level

A Digital On-Line Monitor for Detecting Intermittent Resistance Faults at Board Level

Delay Based Auto-Calibrated PVT Monitor System and Method

Low Overhead and Fast Reaction Adaptive Clocking System for Voltage Droop Tolerance

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